Source虎嗅•Stalecollected in 19m
TSMC Enters Silicon Bridge Packaging Market
TSMC's move to challenge Intel's EMIB tech could significantly lower costs for mid-range AI hardware.
30-Second TL;DR
What Changed
TSMC is diversifying its advanced packaging portfolio by adopting a silicon bridge approach similar to Intel's EMIB.
Why It Matters
This development signals a shift in the advanced packaging landscape, moving from a single-path dominance to a dual-path competition between CoWoS and silicon bridge technologies.
What To Do Next
Evaluate if your hardware roadmap can leverage cost-optimized packaging solutions like quasi-EMIB for future AI inference chips.
Who should care:Developers & AI Engineers
Key Points
- •TSMC is diversifying its advanced packaging portfolio by adopting a silicon bridge approach similar to Intel's EMIB.
- •The move is a strategic response to CoWoS capacity constraints, which have led to long lead times for AI chip customers.
- •The new 'quasi-EMIB' technology targets mid-range AI and high-performance computing, offering a more cost-effective alternative to the premium CoWoS process.
Deep Insight
AI-generated analysis for this event — not the original article.
Enhanced Key Takeaways
- •The 'quasi-EMIB' solution is reportedly referred to internally or within the supply chain as a 'LSI' (Local Silicon Interconnect) derivative, leveraging TSMC's existing 3D Fabric platform capabilities.
- •Kinsus Interconnect Technology is expected to provide the specialized substrate materials and bridge embedding processes required to facilitate the high-density interconnects without the full cost of a silicon interposer.
- •This packaging strategy is specifically designed to support chiplet architectures that require high bandwidth between memory and logic but do not necessitate the extreme density of CoWoS-S or CoWoS-L.
- •Industry analysts suggest this move is a defensive measure to prevent mid-tier AI chip designers from migrating to Intel Foundry or Samsung's I-Cube/H-Cube packaging alternatives due to TSMC's supply bottlenecks.
- •The adoption of a silicon bridge approach allows TSMC to utilize standard organic substrates more effectively, significantly increasing the throughput of their backend packaging lines compared to the complex, interposer-heavy CoWoS process.
Competitor Analysis
Primary Tech
- TSMC (Quasi-EMIB)
- Silicon Bridge (Embedded)
- Intel (EMIB)
- Embedded Multi-die Interconnect Bridge
- Samsung (I-Cube)
- Silicon Interposer
Cost Profile
- TSMC (Quasi-EMIB)
- Mid-Range / Optimized
- Intel (EMIB)
- Premium / High-Performance
- Samsung (I-Cube)
- Variable / Competitive
Target Market
- TSMC (Quasi-EMIB)
- Mid-range AI / HPC
- Intel (EMIB)
- High-end Data Center / AI
- Samsung (I-Cube)
- Broad AI / Mobile / HPC
Maturity
- TSMC (Quasi-EMIB)
- Emerging (2026)
- Intel (EMIB)
- Mature (Industry Standard)
- Samsung (I-Cube)
- Established
| Feature | TSMC (Quasi-EMIB) | Intel (EMIB) | Samsung (I-Cube) |
|---|---|---|---|
| Primary Tech | Silicon Bridge (Embedded) | Embedded Multi-die Interconnect Bridge | Silicon Interposer |
| Cost Profile | Mid-Range / Optimized | Premium / High-Performance | Variable / Competitive |
| Target Market | Mid-range AI / HPC | High-end Data Center / AI | Broad AI / Mobile / HPC |
| Maturity | Emerging (2026) | Mature (Industry Standard) | Established |
Technical Deep Dive
- Utilizes a small silicon bridge embedded within the organic substrate to connect adjacent chiplets.
- Eliminates the need for a large, expensive silicon interposer that spans the entire package area.
- Enables high-speed communication between logic and HBM (High Bandwidth Memory) or between multiple logic dies.
- Compatible with standard flip-chip ball grid array (FCBGA) assembly processes.
- Reduces thermal resistance by minimizing the distance between chiplets and the package substrate.
Future ImplicationsAI analysis grounded in cited sources
TSMC will achieve a 20-30% reduction in packaging costs for mid-range AI chips by 2027.
By shifting away from large silicon interposers to bridge-based interconnects, the material and yield-related costs of advanced packaging are significantly lowered.
Intel Foundry will face increased pricing pressure in the high-performance packaging sector.
TSMC's entry into the silicon bridge market removes Intel's primary technological moat, forcing competitive pricing for EMIB-based packaging services.
Timeline
2011-09
TSMC announces CoWoS (Chip on Wafer on Substrate) technology.
2017-03
Intel introduces EMIB (Embedded Multi-die Interconnect Bridge) as a core packaging innovation.
2021-06
TSMC launches 3D Fabric, an umbrella brand for its advanced packaging and stacking technologies.
2024-05
TSMC reports record-breaking demand for CoWoS, leading to industry-wide capacity constraints.
2026-07
Reports emerge regarding TSMC's collaboration with Kinsus to develop a bridge-based packaging alternative.
- 2011-09TSMC announces CoWoS (Chip on Wafer on Substrate) technology.
- 2017-03Intel introduces EMIB (Embedded Multi-die Interconnect Bridge) as a core packaging innovation.
- 2021-06TSMC launches 3D Fabric, an umbrella brand for its advanced packaging and stacking technologies.
- 2024-05TSMC reports record-breaking demand for CoWoS, leading to industry-wide capacity constraints.
- 2026-07Reports emerge regarding TSMC's collaboration with Kinsus to develop a bridge-based packaging alternative.
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