๐งTom's HardwareโขFreshcollected in 50m
Synopsys Demonstrates PCIe 6.0 in 3D Stacking
๐กA validated 64 GT/s 3D PHY could shape bandwidth planning for future AI accelerator systems.
โก 30-Second TL;DR
What Changed
Synopsys reports silicon validation of a 3D PCIe 6.0 test chip.
Why It Matters
Higher-bandwidth, compact interconnects could eventually benefit AI accelerator, memory, and advanced packaging systems. However, the result is a technology validation rather than an immediately deployable AI product.
What To Do Next
Ask your hardware team to evaluate PCIe 6.0 and 3D-packaging roadmaps when planning the next generation of accelerator or high-bandwidth inference systems.
Who should care:Researchers & Academics
Key Points
- โขSynopsys reports silicon validation of a 3D PCIe 6.0 test chip.
- โขThe design integrates a 5nm PHY into a face-to-face 3D stacked package.
- โขThe interconnect operates at 64 GT/s.
๐ง Deep Insight
Background and context from public sources โ not the original article. 15 sources cited.
๐ Enhanced Key Takeaways
- โขThe 3D PCIe 6.0 test chip utilizes through-silicon vias (TSVs) to route signals to the package, a significant architectural shift from traditional monolithic or 2.5D designs where PHYs are typically located at the die's perimeter.
- โขSynopsys developed this 3D PCIe 6.0 solution by adapting an existing 2D PCIe 6.0 test chip, integrating TSVs, and performing circuit redesign and signoff specifically for 3D process design kits.
- โขFace-to-face hybrid bonding in 3D stacking introduces a unique challenge for PCIe PHY placement, as the PHYs face away from the package substrate, necessitating complex signal routing through vias and up to upper metal layers before descending.
- โขPCIe 6.0 achieves its doubled signaling rate of 64 GT/s per lane over PCIe 5.0 by employing PAM4 (Pulse Amplitude Modulation with 4 levels) signaling, coupled with FLIT-based transmission and mandatory Forward Error Correction (FEC) to manage the higher bit error rates inherent to PAM4.
- โขThe adoption of 3D stacking for high-speed interconnects like PCIe 6.0 offers substantial benefits, including increased performance, reduced power consumption, a smaller form factor, and the potential for up to 100x higher I/O density by minimizing physical distances between stacked dies.
๐ ๏ธ Technical Deep Dive
- PCIe 6.0 utilizes PAM4 (Pulse Amplitude Modulation with 4 levels) signaling, which encodes 2 bits per symbol, effectively doubling the bandwidth per lane compared to the NRZ signaling used in previous PCIe generations.
- To counteract the significantly higher raw Bit Error Rate (BER) associated with PAM4 signaling, PCIe 6.0 introduces FLIT (Flow control unIT) mode and mandatory Forward Error Correction (FEC).
- In FLIT mode, data is transmitted in fixed 256-byte units, comprising 236 bytes of payload and 8 bytes of CRC (CRC-9), which, along with FEC, provides more efficient error correction than the TLP-based framing of earlier PCIe versions.
- The 3D stacked design routes high-speed signals through Through-Silicon Vias (TSVs) to the package, requiring specialized circuit design and signoff processes tailored for 3D process design kits.
- Synopsys's 5nm PHY incorporates unique adaptive DSP algorithms to optimize analog and digital equalization, enhancing power efficiency, and features patent-pending diagnostic capabilities for near-zero link downtime.
- The PHY's placement-aware architecture is designed to minimize package crosstalk and facilitate dense SoC integration for x16 links, achieving ultra-low latency through an optimized ADC-based datapath.
- PCIe 6.0 also introduces the L0p low-power state, which is exclusively enabled in FLIT mode and conserves power by allowing traffic to run on fewer active lanes while ensuring at least one lane remains operational.
๐ฎ Future ImplicationsAI analysis grounded in cited sources
The successful validation of 3D PCIe 6.0 will accelerate the adoption of multi-die chip designs in high-performance computing (HPC) and artificial intelligence (AI) applications.
3D stacking offers critical advantages such as increased performance, reduced power consumption, and smaller form factors, which are essential for the demanding requirements of AI data centers and HPC.
This technology will lead to the development of more power-efficient and higher-density interconnects for next-generation data centers.
3D-ICs reduce the physical distance between dies, enabling faster data exchange with lower energy consumption and significantly higher I/O density compared to 2D designs.
The engineering challenges overcome in implementing 3D PCIe 6.0 will establish a robust methodology for the faster development and integration of future PCIe generations within advanced packaging technologies.
Synopsys's approach of adapting an existing 2D design for 3D stacking provides a proven pathway for addressing complex signal integrity and routing issues in advanced multi-die packages.
โณ Timeline
2021-03
Synopsys announces the industry's first complete IP solution for PCIe 6.0, including controller, PHY, and verification IP.
2022-01
PCI-SIG releases the original PCIe 6.0 specification, doubling the data rate to 64 GT/s.
2023-02
Synopsys and Keysight demonstrate a two-party linkup of Synopsys PCIe 6.0 IP, validating interoperability at 64 GT/s.
2026-08
Synopsys publishes silicon results for the first 3D PCIe 6.0 test chip, demonstrating a 5nm PHY in a face-to-face stacked package at 64 GT/s.
๐ Sources (15)
Factual claims are grounded in the sources below. Forward-looking analysis is AI-generated interpretation.
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