Fujitsu shows 144-core MONAKA CPU sample
💡144-core 3.5D CPU sample for HPC – key for AI infra builders
⚡ 30-Second TL;DR
What Changed
144 cores in new MONAKA CPU architecture
Why It Matters
Advances high-core density CPUs for AI/HPC workloads, potentially lowering costs for scalable data centers. Fujitsu's progress signals competition in AI infrastructure hardware.
What To Do Next
Benchmark MONAKA samples against ARM-based HPC alternatives for your data center upgrades.
Key Points
- •144 cores in new MONAKA CPU architecture
- •3.5D packaging for data center and HPC
- •First wafers and samples shown at MWC 2026
- •Joint demo with 1FINITY network vendor
- •Processor now in runnable engineering phase
🧠 Deep Insight
Background and context from public sources — not the original article. 6 sources cited.
🔑 Enhanced Key Takeaways
- •Monaka uses four 36-core compute chiplets on TSMC's 2nm process stacked face-to-face via hybrid copper bonding on 5nm SRAM tiles.[1][2]
- •Features a central I/O die with 12-channel DDR5 memory controller, PCIe 6.0 with CXL 3.0 support, and no HBM integration.[1][3]
- •Developed in collaboration with Broadcom using 3.5D XDSiP platform, targeting air-cooling for doubled energy efficiency by 2026-2027.[2]
- •Armv9-A with SVE2 for AI/HPC and Confidential Computing; supports up to 6TB DDR5 RDIMM per node in dual-socket configs.[3][4]
📊 Competitor Analysis▸ Show
| Feature | Fujitsu Monaka (144-core) | AMD EPYC (e.g., Genoa-X) | Intel Xeon (e.g., Emerald Rapids) |
|---|---|---|---|
| Cores per Socket | 144 Armv9 | Up to 192 Zen4 | Up to 64 Sapphire Rapids |
| Process Node | 2nm cores + 5nm SRAM/IO | 5nm/4nm | Intel 7 (≈5nm) |
| Packaging | 3D chiplet CoWoS/XDSiP, air-cooling | 2.5D/3D V-Cache | 2.5D EMIB |
| Memory | 12-ch DDR5, up to 6TB/node | 12-ch DDR5 | 8-ch DDR5 |
| Efficiency Goal | Double competitors by 2026-2027 | High perf/watt | Optimized for enterprise |
🛠️ Technical Deep Dive
- •Architecture: Armv9-A with SVE2 (256-bit) for AI/HPC acceleration and Confidential Computing for security.[3][4]
- •Chiplet Design: 4x 36-core compute dies (TSMC N2) stacked F2F on SRAM dies (TSMC N5) using hybrid copper bonding (HCB); central I/O die handles interfaces.[1][2][5]
- •Memory: 12-channel DDR5 RDIMM controller supporting up to 6TB per dual-socket node (21GB/core), bandwidth ~460-1228 GB/s with future MCRDIMMs.[1][3]
- •I/O: PCIe 6.0 x16 (CXL 3.0) low-profile slots (2-5 per node), OCP 3.0 NIC, InfiniBand/Ethernet interconnects; supports 2 full-size GPGPUs.[3]
- •Power/Cooling: Ultra-low voltage operation with air-cooling capability; 2nm cores <30% of total die area for cost efficiency.[4]
- •Dual-socket: 288 cores/node, 24 DIMM slots, 2U chassis with water-cooling option for CPU.[3]
🔮 Future ImplicationsAI analysis grounded in cited sources
⏳ Timeline
📎 Sources (6)
Factual claims are grounded in the sources below. Forward-looking analysis is AI-generated interpretation.
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