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Fujitsu shows 144-core MONAKA CPU sample

Fujitsu shows 144-core MONAKA CPU sample
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๐Ÿ’ก144-core 3.5D CPU sample for HPC โ€“ key for AI infra builders

โšก 30-Second TL;DR

What Changed

144 cores in new MONAKA CPU architecture

Why It Matters

Advances high-core density CPUs for AI/HPC workloads, potentially lowering costs for scalable data centers. Fujitsu's progress signals competition in AI infrastructure hardware.

What To Do Next

Benchmark MONAKA samples against ARM-based HPC alternatives for your data center upgrades.

Who should care:Enterprise & Security Teams

๐Ÿง  Deep Insight

Web-grounded analysis with 6 cited sources.

๐Ÿ”‘ Enhanced Key Takeaways

  • โ€ขMonaka uses four 36-core compute chiplets on TSMC's 2nm process stacked face-to-face via hybrid copper bonding on 5nm SRAM tiles.[1][2]
  • โ€ขFeatures a central I/O die with 12-channel DDR5 memory controller, PCIe 6.0 with CXL 3.0 support, and no HBM integration.[1][3]
  • โ€ขDeveloped in collaboration with Broadcom using 3.5D XDSiP platform, targeting air-cooling for doubled energy efficiency by 2026-2027.[2]
  • โ€ขArmv9-A with SVE2 for AI/HPC and Confidential Computing; supports up to 6TB DDR5 RDIMM per node in dual-socket configs.[3][4]
๐Ÿ“Š Competitor Analysisโ–ธ Show
FeatureFujitsu Monaka (144-core)AMD EPYC (e.g., Genoa-X)Intel Xeon (e.g., Emerald Rapids)
Cores per Socket144 Armv9Up to 192 Zen4Up to 64 Sapphire Rapids
Process Node2nm cores + 5nm SRAM/IO5nm/4nmIntel 7 (โ‰ˆ5nm)
Packaging3D chiplet CoWoS/XDSiP, air-cooling2.5D/3D V-Cache2.5D EMIB
Memory12-ch DDR5, up to 6TB/node12-ch DDR58-ch DDR5
Efficiency GoalDouble competitors by 2026-2027High perf/wattOptimized for enterprise

๐Ÿ› ๏ธ Technical Deep Dive

  • โ€ขArchitecture: Armv9-A with SVE2 (256-bit) for AI/HPC acceleration and Confidential Computing for security.[3][4]
  • โ€ขChiplet Design: 4x 36-core compute dies (TSMC N2) stacked F2F on SRAM dies (TSMC N5) using hybrid copper bonding (HCB); central I/O die handles interfaces.[1][2][5]
  • โ€ขMemory: 12-channel DDR5 RDIMM controller supporting up to 6TB per dual-socket node (21GB/core), bandwidth ~460-1228 GB/s with future MCRDIMMs.[1][3]
  • โ€ขI/O: PCIe 6.0 x16 (CXL 3.0) low-profile slots (2-5 per node), OCP 3.0 NIC, InfiniBand/Ethernet interconnects; supports 2 full-size GPGPUs.[3]
  • โ€ขPower/Cooling: Ultra-low voltage operation with air-cooling capability; 2nm cores <30% of total die area for cost efficiency.[4]
  • โ€ขDual-socket: 288 cores/node, 24 DIMM slots, 2U chassis with water-cooling option for CPU.[3]

๐Ÿ”ฎ Future ImplicationsAI analysis grounded in cited sources

Monaka enables air-cooled 288-core Arm nodes with 6TB DDR5 at lower cost than HBM-based rivals.
3D stacking limits 2nm to cores only while using cost-effective 5nm for SRAM/IO and mainstream DDR5 avoids HBM shortages and high costs.[1][4]
Fujitsu targets 2x energy efficiency over x86 competitors by 2026-2027 via ultra-low voltage Armv9.
Monaka's design emphasizes low power with air cooling, SVE2 optimizations, and advanced nodes to outperform AMD EPYC and Intel Xeon in datacenter efficiency.[2][4]

โณ Timeline

2024-01
Fujitsu announces MONAKA as successor to A64FX with 3D chiplet design on 2nm/5nm.
2024-12
Fujitsu details MONAKA specs including Armv9-A, 144 cores x2 sockets, DDR5 in public presentation.
2025-01
Fujitsu presents MONAKA technologies at ISC 2025 with OSS compiler activities.
2026-02
Announces partnership with Broadcom for 3.5D XDSiP platform for MONAKA.
2026-03
Showcases first wafers, engineering samples at MWC 2026 with 1FINITY demo; enters runnable phase.
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