Chip Startup Euclyd Seeks €200M in Series A Funding
💡New semiconductor ventures backed by ASML leadership are critical signals for the future of AI hardware.
⚡ 30-Second TL;DR
What Changed
Euclyd seeking €200 million in Series A financing
Why It Matters
New semiconductor players backed by industry veterans often signal breakthroughs in chip architecture, potentially impacting future AI hardware supply chains.
What To Do Next
Follow Euclyd's technical whitepapers or patent filings to identify potential shifts in chip architecture for AI acceleration.
Key Points
- •Euclyd seeking €200 million in Series A financing
- •Backed by former ASML CEO Peter Wennink
- •Focus on advanced semiconductor technology development
🧠 Deep Insight
AI-generated analysis for this event — not the original article.
🔑 Enhanced Key Takeaways
- •Euclyd is specifically targeting the development of next-generation photonic computing architectures to overcome traditional CMOS scaling limitations.
- •The startup is headquartered in Eindhoven, Netherlands, strategically positioning itself within the high-tech ecosystem surrounding ASML and Philips.
- •Peter Wennink joined Euclyd as a strategic advisor and investor shortly after his departure from ASML in early 2024.
- •The company's proprietary technology focuses on reducing energy consumption in AI data centers by utilizing light-based interconnects instead of copper wiring.
- •Euclyd has reportedly secured preliminary interest from European venture capital firms specializing in deep tech and sovereign semiconductor independence.
📊 Competitor Analysis▸ Show
| Competitor | Focus Area | Key Advantage |
|---|---|---|
| Lightmatter | Photonic AI Accelerators | Established market presence and high-speed interconnects |
| Ayar Labs | Optical I/O Chiplets | Strong partnerships with major foundries like GlobalFoundries |
| Luminous | Photonic Computing | Advanced silicon photonics integration for LLMs |
🛠️ Technical Deep Dive
- Architecture: Utilizes silicon photonics to perform matrix-vector multiplication in the optical domain.
- Interconnects: Implements chip-to-chip optical I/O to reduce latency and power dissipation in large-scale AI clusters.
- Manufacturing: Designed for compatibility with standard CMOS fabrication processes to facilitate rapid scaling.
- Power Efficiency: Targets a 10x reduction in energy-per-bit compared to electrical SerDes (Serializer/Deserializer) interfaces.
🔮 Future ImplicationsAI analysis grounded in cited sources
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Original source: Bloomberg Technology ↗
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