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Zen6 Leaks with 10 Cores, 32MB L3

Zen6 Leaks with 10 Cores, 32MB L3
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๐Ÿ‡จ๐Ÿ‡ณRead original on cnBeta (Full RSS)
#geekbench-leak#mobile-cpu#l3-cacheamd-zen6amdzen6

๐Ÿ’กZen6's odd 10-core mobile design hints at future AI laptop chips

โšก 30-Second TL;DR

What Changed

First sighting in Geekbench 6 database

Why It Matters

Signals AMD's next-gen mobile CPU push, potentially impacting AI edge devices and laptops.

What To Do Next

Benchmark Zen6 leaks in Geekbench to compare against current Zen5 mobile performance.

Who should care:Researchers & Academics

Key Points

  • โ€ขFirst sighting in Geekbench 6 database
  • โ€ขEngineering sample: 'Plum-MDS1' (Medusa Point mobile platform)
  • โ€ขFeatures 10-core CPU with 32MB L3 cache

๐Ÿง  Deep Insight

Background and context from public sources โ€” not the original article. 4 sources cited.

๐Ÿ”‘ Enhanced Key Takeaways

  • โ€ขZen 6 codenamed 'Morpheus' features single-chiplet models in 6, 8, 10, and 12-core variants, with dual-chiplet options up to 24 cores (12+12).[1]
  • โ€ขArchitecture built on TSMC 2nm or 3nm process with 8-wide dispatch engine, SMT, and each 12-core CCD having 48MB L3 cache.[1][2]
  • โ€ขAdopts Intel's FRED interrupt handling and introduces native FP16 support for AI workloads.[1][3]

๐Ÿ› ๏ธ Technical Deep Dive

  • โ€ขGround-up redesign on TSMC 2nm-class process, featuring eight-slot dispatch engine for throughput-oriented design with simultaneous multi-threading (SMT).[2]
  • โ€ข12-core CCD configuration with 48MB L3 cache per CCD, enabling up to 96MB total on 24-core models before 3D V-Cache.[1]
  • โ€ขSupports new instructions including native FP16 handling to accelerate AI and machine learning workloads.[1]
  • โ€ขIncorporates FRED (Flexible Rapid Event Delivery) interrupt handling, originally from Intel, for improved exception handling and speed.[3]

๐Ÿ”ฎ Future ImplicationsAI analysis grounded in cited sources

Zen 6 desktop Ryzen launch delayed to 2027
Reports indicate prioritization of Zen 6 for EPYC server chips in 2026 due to industry focus on data centers amid rising costs.[4]
Major IPC and efficiency gains from 2nm node
Shift to advanced TSMC 2nm process enables higher core density, better clocks, and architectural improvements like wider dispatch.[1][2]
Competitive parity in interrupt handling
Adoption of Intel's FRED technology standardizes performance benefits across x86 ecosystem.[3]

โณ Timeline

2026-03
Zen 6 'Plum-MDS1' 10-core mobile engineering sample appears in Geekbench 6 database.
2026-03
AMD publishes first Zen 6 developer documentation detailing 8-wide core and FRED support.
2026-01
Leaks reveal Zen 6 'Morpheus' core counts from 6 to 24 and 2nm architecture details.
๐Ÿ“ฐ

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