🐯虎嗅•Stalecollected in 22m
TSMC Delays High-NA EUV to 2029
💡TSMC skips $410M litho—reshapes AI chip fab timelines
⚡ 30-Second TL;DR
What Changed
High-NA EUV costs $410M per unit, twice current EUV
Why It Matters
Slows global advanced AI chip node race; boosts TSMC margins but risks lag vs rivals.
What To Do Next
Optimize your multi-patterning flows in existing EUV sims for AI chip design.
Who should care:Developers & AI Engineers
Key Points
- •High-NA EUV costs $410M per unit, twice current EUV
- •TSMC to multi-expose with existing EUV for node shrinks
- •Intel/Samsung adopt aggressively; TSMC prioritizes margins
🧠 Deep Insight
AI-generated analysis for this event.
🔑 Enhanced Key Takeaways
- •TSMC's strategy relies on 'EUV 0.33 NA' optimization, specifically leveraging advanced computational lithography and improved resist materials to extend the life of current machines beyond the 2nm node.
- •The decision to delay High-NA is influenced by the significant increase in power consumption and cleanroom height requirements (the 'fab ceiling' issue) necessitated by the larger ASML EXE:5200 machines.
- •Industry analysts suggest TSMC's move is a calculated risk to avoid the 'yield valley' associated with early adoption of High-NA, allowing Intel and Samsung to bear the initial R&D and process integration costs.
📊 Competitor Analysis▸ Show
| Feature | TSMC (A16/A13) | Intel (14A) | Samsung (SF1.4) |
|---|---|---|---|
| High-NA Adoption | Delayed (2029) | Early Adopter (2025+) | Early Adopter (2026+) |
| Primary Strategy | EUV 0.33 NA Optimization | High-NA EUV Integration | High-NA EUV Integration |
| Cost Profile | Margin-focused/Conservative | High CapEx/Aggressive | High CapEx/Aggressive |
🛠️ Technical Deep Dive
- High-NA EUV (0.55 NA) utilizes a larger numerical aperture to achieve a resolution of 8nm, compared to 13nm for standard 0.33 NA EUV.
- The transition to High-NA requires anamorphic lenses, which result in a smaller exposure field (26mm x 16mm) compared to standard EUV (26mm x 33mm), necessitating complex 'stitching' techniques for large-die chips.
- TSMC's alternative, multi-patterning with 0.33 NA, increases mask counts and process steps, which TSMC aims to mitigate through proprietary 'Super-High-NA' computational lithography software.
🔮 Future ImplicationsAI analysis grounded in cited sources
TSMC will face increased mask costs for nodes between 2nm and 1.4nm.
Relying on multi-patterning with 0.33 NA EUV instead of single-exposure High-NA inherently requires more masks per layer, increasing production complexity.
Intel's foundry business will gain a temporary technical advantage in feature density.
By adopting High-NA earlier, Intel can achieve smaller feature sizes in a single exposure, potentially offering higher transistor density for logic-heavy AI accelerators.
⏳ Timeline
2022-07
TSMC confirms it is evaluating High-NA EUV but emphasizes the maturity of 0.33 NA systems.
2023-12
ASML ships the first High-NA EUV (EXE:5000) system to Intel for R&D.
2024-04
TSMC announces A16 process node, focusing on backside power delivery without immediate High-NA requirements.
2025-09
TSMC begins volume production of 2nm (N2) using standard 0.33 NA EUV.
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