Kioxia Discontinues TSOP MLC NAND
๐กNAND supply crunch on legacy chips could impact AI prototype hardware costs
โก 30-Second TL;DR
What Changed
Targets TSOP thin small-outline package MLC NAND
Why It Matters
May disrupt legacy embedded AI devices using compact storage, pushing adoption of higher-density NAND alternatives.
What To Do Next
Inventory TSOP MLC in edge AI hardware and test Kioxia BiCS 3D NAND replacements.
Key Points
- โขTargets TSOP thin small-outline package MLC NAND
- โขCovers 8Gb-64Gb small-capacity storage chips
- โขDriven by production capacity and substrate shortages
๐ง Deep Insight
Background and context from public sources โ not the original article. 7 sources cited.
๐ Enhanced Key Takeaways
- โขKioxia has established a strict EOL (End-of-Life) schedule: last forecasted orders are due by May 30, 2026, with a final order cutoff on September 15, 2026, and final shipments concluding by March 15, 2027.
- โขThe discontinuation is part of a broader industry-wide '2D NAND exit'; global MLC capacity is projected to decline by 41.7% year-over-year in 2026 as major fabs convert legacy lines to DRAM or high-layer 3D NAND.
- โขThe 'substrate shortage' cited specifically refers to the declining availability of lead-frame and resin materials for legacy 'Slim NAND' packages as suppliers pivot to high-margin FC-BGA and substrate-like PCB (SLP) technologies.
- โขKioxia is reallocating the freed-up wafer capacity to fulfill massive long-term agreements (LTAs) with hyperscalers for BiCS8 and BiCS10 3D NAND, which the company confirmed are already 'sold out' through the end of 2026.
๐ Competitor Analysisโธ Show
| Competitor | Strategy | Status |
|---|---|---|
| Samsung | Full Exit | Discontinued 2D NAND/MLC in Q1 2026 to convert Hwaseong Line 12 to 1C DRAM. |
| Macronix | Market Expansion | Ramping up MLC production to capture legacy industrial share, though at the cost of NOR flash capacity. |
| Micron | Restricted Supply | Limiting MLC production strictly to existing long-term contractual obligations for industrial clients. |
| SK Hynix | Strategic Pivot | Prioritizing HBM and high-layer 3D NAND (300+ layers) over legacy planar MLC products. |
๐ ๏ธ Technical Deep Dive
Detailed technical specifications for the discontinued Kioxia MLC series:
- Process Node: 15nm Planar (2D) process technology.
- Package Type: 48-pin TSOP-I (Thin Small Outline Package), Type I.
- Interface: Supports Toggle 2.0 and legacy Open NAND Flash Interface (ONFI) standards.
- Voltage Requirements: 3.3V Vcc (standard for legacy industrial and embedded systems).
- Reliability: Requires external controller-based Error Correction Code (ECC) of 40-bit to 72-bit per 1KB.
- Architecture: 2-bit-per-cell Multi-Level Cell (MLC) with 16K page size support.
๐ฎ Future ImplicationsAI analysis grounded in cited sources
โณ Timeline
๐ Sources (7)
Factual claims are grounded in the sources below. Forward-looking analysis is AI-generated interpretation.
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Original source: cnBeta (Full RSS) โ
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