🐯虎嗅•Stalecollected in 24m
Keller: RISC-V CPU-AI Fusion Inevitable
💡RISC-V 4x ARM designs; Tenstorrent CPU-AI roadmap drops costs
⚡ 30-Second TL;DR
What Changed
RISC-V新設計20+，ARM 5、Intel 2
Why It Matters
RISC-V erodes ARM/Intel dominance, cuts AI compute costs with open high-perf chips.
What To Do Next
Test Tenstorrent BUDA toolchain for RISC-V AI model deployment.
Who should care:Developers & AI Engineers
Key Points
- •RISC-V新設計20+，ARM 5、Intel 2
- •Ascalon：8路解碼、6 ALU、2x256-bit向量、230GB/s
- •路線圖：Grendel CPU+ML chiplets融合
- •BUDA自動化AI程式，Android官方支援RISC-V
🧠 Deep Insight
AI-generated analysis for this event.
🔑 Enhanced Key Takeaways
- •Tenstorrent's strategy leverages the 'chiplet' ecosystem to decouple CPU core development from AI accelerator silicon, allowing for rapid iteration of heterogeneous compute tiles.
- •The BUDA software stack is designed to abstract hardware complexity by compiling high-level AI models (PyTorch/TensorFlow) directly into a graph-based intermediate representation that maps across both RISC-V cores and Tenstorrent's proprietary Tensix cores.
- •RISC-V's momentum is bolstered by the 'RISE' (RISC-V Software Ecosystem) project, which coordinates industry-wide efforts to upstream RISC-V support into major Linux distributions and toolchains, reducing the fragmentation risk historically associated with open-source architectures.
📊 Competitor Analysis▸ Show
| Feature | Tenstorrent (Ascalon/Grendel) | ARM (Neoverse V3) | Intel (Xeon 6 / Gaudi 3) |
|---|---|---|---|
| ISA | RISC-V (Open) | ARMv9 (Proprietary) | x86-64 (Proprietary) |
| AI Integration | Native Chiplet Fusion | External/PCIe Accelerator | Integrated AMX / Gaudi PCIe |
| Customization | High (Instruction Set Extensions) | Low (Licensing constraints) | Low (Fixed architecture) |
| Software Stack | BUDA (Graph-based) | Standard Linux/Compute Libs | OneAPI / OpenVINO |
🛠️ Technical Deep Dive
- Ascalon Core Architecture: Features an out-of-order execution engine with an 8-wide decode width, designed to maximize IPC (Instructions Per Cycle) for high-performance server workloads.
- Vector Processing: Utilizes dual 256-bit vector units per core, optimized for AI inference and mathematical acceleration, bridging the gap between general-purpose CPU tasks and specialized NPU tasks.
- Interconnect: Employs a high-bandwidth chiplet-to-chiplet interconnect (likely based on UCIe or proprietary low-latency fabric) to achieve the 230GB/s bandwidth, minimizing data movement bottlenecks between the CPU and AI compute tiles.
- BUDA Compiler: Implements a 'graph-to-hardware' mapping approach that treats the entire chiplet array as a unified compute fabric, automatically partitioning tensors across available RISC-V and Tensix cores.
🔮 Future ImplicationsAI analysis grounded in cited sources
RISC-V will capture >20% of the hyperscaler server CPU market by 2030.
The combination of open-source ISA flexibility and the ability to integrate custom AI accelerators provides a cost-to-performance advantage that proprietary architectures struggle to match.
Tenstorrent will transition to a pure-play IP and chiplet provider model.
The company's focus on licensing Ascalon cores and BUDA software suggests a shift away from selling finished silicon toward enabling other vendors to build custom AI-CPU fusion chips.
⏳ Timeline
2016-05
Tenstorrent founded by Ljubisa Bajic, Ivan Hamer, and Milos Trajkovic.
2023-01
Jim Keller appointed as CEO of Tenstorrent.
2023-08
Tenstorrent announces the Ascalon RISC-V high-performance CPU core.
2024-02
Tenstorrent and LG Electronics announce partnership to integrate RISC-V and AI into smart TVs and automotive products.
2025-06
Tenstorrent demonstrates Grendel chiplet-based architecture for AI-CPU fusion.
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