SetupAI
繁
SourceStalecollected in 58m

Imec, TSMC, ASML achieve 50nm 2D material transistor integration

Read original on IT之家
#semiconductor#hardware#euv#nanotechnology

A major hardware breakthrough enabling the next generation of high-density, energy-efficient AI chips.

30-Second TL;DR

What Changed

First successful integration of 2D CMOS on standard 300mm wafer process

Why It Matters

This milestone accelerates the roadmap for post-silicon logic chips, potentially enabling smaller, more efficient transistors for future AI hardware.

What To Do Next

Track the IRDS roadmap for 2D semiconductors to anticipate when these materials will impact high-performance AI chip design.

Who should care:Researchers & Academics

Key Points

  • •First successful integration of 2D CMOS on standard 300mm wafer process
  • •Achieved 50nm contacted gate pitch (CPP) using single-exposure EUV lithography
  • •Used MoS2 for n-type and WSe2/WS2 for p-type channels to improve gate control

Deep Insight

AI-generated analysis for this event — not the original article.

Enhanced Key Takeaways

  • •The integration utilized a 'gate-last' integration scheme, which is critical for maintaining the integrity of 2D material channels during high-temperature processing steps.
  • •Researchers successfully demonstrated the use of semi-metallic contacts (such as Bismuth or Antimony) to reduce the Schottky barrier height, addressing the historically difficult contact resistance issue in 2D materials.
  • •The process flow incorporated a specialized transfer-free growth or direct deposition technique to ensure uniform monolayer coverage across the 300mm wafer surface.
  • •This achievement specifically addresses the 'short-channel effect' challenges that typically plague sub-50nm devices by leveraging the atomically thin nature of TMDs (Transition Metal Dichalcogenides).
  • •The collaboration utilized ASML's high-NA EUV lithography capabilities to achieve the precise patterning required for the 50nm contacted gate pitch (CPP) without damaging the delicate 2D layers.

Technical Deep Dive

  • Channel Materials: Monolayer MoS2 (n-type) and WSe2/WS2 (p-type) were utilized to form the CMOS inverter structure.
  • Gate Pitch: 50nm Contacted Gate Pitch (CPP) achieved via single-exposure EUV lithography.
  • Contact Engineering: Implementation of semi-metallic contact electrodes to minimize contact resistance, a primary bottleneck for 2D material performance.
  • Integration Scheme: Gate-last process flow on 300mm Si/SiO2 wafers to prevent thermal degradation of the 2D channel materials.
  • Lithography: Use of EUV patterning to define gate electrodes with high precision, essential for scaling below the 50nm threshold.

Future ImplicationsAI analysis grounded in cited sources

2D materials will enter pilot production lines by 2028.
The successful demonstration on 300mm wafers proves compatibility with existing CMOS manufacturing infrastructure, reducing the barrier to industrial adoption.
TMD-based transistors will replace FinFETs in sub-2nm logic nodes.
The superior electrostatic control of atomically thin 2D channels allows for continued scaling where traditional silicon FinFETs suffer from severe leakage and short-channel effects.

Timeline

2021-06
Imec demonstrates first functional 2D material-based transistors on 300mm wafers.
2023-12
Imec and partners report breakthroughs in contact resistance reduction for MoS2 channels.
2025-04
TSMC and Imec announce joint research expansion into 2D material integration for advanced logic.
2026-06
Successful integration of n-type and p-type 2D transistors at 50nm CPP.
Read original article on IT之家

Weekly AI Recap

Read this week's curated digest of top AI events →

PostLinkedIn

AI-curated news aggregator. All content rights belong to original publishers.
Original source: IT之家 ↗

This is a summary, not the original. Read the source, or get the weekly briefing.

The weekly digest

One email a week. Unsubscribe anytime.