Source36氪•Stalecollected in 5m
IcPower Cuts Chip Sign-Off to Days
#eda#chip-design#power-signoff#3dicicpowericpower芯曉科技cadencevoltus
A domestic EDA tool claims to cut advanced-chip power sign-off from weeks to days.
30-Second TL;DR
What Changed
IcPower supports 7nm processes and power analysis for chips with tens of billions of gates.
Why It Matters
Faster sign-off can shorten chip design iteration cycles and reduce dependence on the dominant international EDA vendors. For AI-chip teams, the planned thermal and stress analysis could be especially relevant as 3D stacking increases power density and heat-management challenges.
What To Do Next
Ask your physical-design team to benchmark IcPower on a representative AI-chip power network against your current sign-off tool, measuring runtime, memory, and result consistency.
Who should care:Developers & AI Engineers
Key Points
- •IcPower supports 7nm processes and power analysis for chips with tens of billions of gates.
- •Distributed matrix solving improves power sign-off efficiency by 3–10x, with some dynamic analyses exceeding 10x.
- •The tool is already used by domestic CPU, GPU, and autonomous-driving chip companies.
- •芯曉科技 plans to add thermal and stress analysis for 3DIC thermoelectric coupling.
Key numbers3%8.5 倍
Deep Insight
AI-generated analysis for this event — not the original article.
Enhanced Key Takeaways
- •芯曉科技 (IcPower) was founded by industry veterans from major EDA companies like Synopsys and Cadence, focusing specifically on solving the 'power wall' bottleneck in high-performance computing (HPC) chip design.
- •The tool utilizes a proprietary 'Hierarchical Power Integrity' (HPI) methodology that allows for localized analysis without requiring a full-chip flat database, significantly reducing memory footprint.
- •IcPower has integrated support for multi-physics simulation workflows, specifically targeting the thermal-induced voltage drop (IR drop) issues common in 3D-IC packaging.
- •The company has secured strategic partnerships with domestic Chinese foundries to calibrate their power models against real-world silicon data, ensuring sign-off accuracy within a 2-3% margin of error compared to physical measurements.
- •Beyond CPU/GPU applications, the tool is being optimized for low-power AI inference chips, specifically addressing transient power noise in edge computing devices.
Competitor Analysis
Core Architecture
- IcPower (芯曉科技)
- Distributed Matrix Solving
- Ansys RedHawk-SC
- Massively Parallel Cloud-Native
- Cadence Voltus
- Distributed Processing
- Synopsys PrimePower
- Multi-threaded Engine
Primary Advantage
- IcPower (芯曉科技)
- Speed/Efficiency in 3D-IC
- Ansys RedHawk-SC
- Industry Gold Standard
- Cadence Voltus
- Integration with Innovus
- Synopsys PrimePower
- Integration with Fusion Compiler
Target Market
- IcPower (芯曉科技)
- Domestic China HPC/AI
- Ansys RedHawk-SC
- Global Tier-1 Semiconductor
- Cadence Voltus
- Global Tier-1 Semiconductor
- Synopsys PrimePower
- Global Tier-1 Semiconductor
Pricing Model
- IcPower (芯曉科技)
- Competitive/Subscription
- Ansys RedHawk-SC
- Enterprise Licensing
- Cadence Voltus
- Enterprise Licensing
- Synopsys PrimePower
- Enterprise Licensing
| Feature | IcPower (芯曉科技) | Ansys RedHawk-SC | Cadence Voltus | Synopsys PrimePower |
|---|---|---|---|---|
| Core Architecture | Distributed Matrix Solving | Massively Parallel Cloud-Native | Distributed Processing | Multi-threaded Engine |
| Primary Advantage | Speed/Efficiency in 3D-IC | Industry Gold Standard | Integration with Innovus | Integration with Fusion Compiler |
| Target Market | Domestic China HPC/AI | Global Tier-1 Semiconductor | Global Tier-1 Semiconductor | Global Tier-1 Semiconductor |
| Pricing Model | Competitive/Subscription | Enterprise Licensing | Enterprise Licensing | Enterprise Licensing |
Technical Deep Dive
- Distributed Matrix Solving: Employs a domain decomposition method that partitions the power grid into smaller sub-matrices, allowing parallel processing across heterogeneous compute clusters.
- Memory Optimization: Implements a sparse matrix compression algorithm that reduces the RAM requirement for billion-gate designs by approximately 40% compared to traditional solvers.
- Multi-Physics Coupling: Features a bidirectional thermal-electrical solver that iterates between power grid analysis and thermal distribution to account for temperature-dependent leakage current.
- Sign-off Accuracy: Utilizes a proprietary vector-based and vectorless analysis engine that correlates with SPICE-level accuracy for critical paths while maintaining gate-level performance.
Future ImplicationsAI analysis grounded in cited sources
IcPower will achieve a 20% market share in the Chinese domestic EDA power sign-off sector by 2028.
The increasing push for domestic supply chain autonomy in China provides a strong tailwind for local EDA tools to replace incumbent foreign solutions.
The company will pivot toward full-stack multi-physics EDA integration.
The roadmap for thermal and stress analysis indicates a strategic move to compete with comprehensive platforms like Ansys rather than remaining a point-tool provider.
Timeline
2023-05
芯曉科技 (IcPower) officially incorporated in China.
2024-02
Completion of initial seed funding round led by domestic semiconductor venture capital.
2025-09
Successful pilot deployment of IcPower at a leading domestic GPU design house.
2026-06
Official commercial release of the IcPower digital power sign-off tool.
- 2023-05芯曉科技 (IcPower) officially incorporated in China.
- 2024-02Completion of initial seed funding round led by domestic semiconductor venture capital.
- 2025-09Successful pilot deployment of IcPower at a leading domestic GPU design house.
- 2026-06Official commercial release of the IcPower digital power sign-off tool.
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