🏠IT之家•Freshcollected in 6m
Chinese RapidIO Chips Successfully Power On
#ai-interconnect#rapidio#pcie-4#rdma井芯微-sr1820-/-st0420井芯微sr1820st0420rapidiogpu direct rdma
💡A new domestic RapidIO–PCIe pair targets 40Gbps+ GPU Direct RDMA for AI clusters.
⚡ 30-Second TL;DR
What Changed
SR1820 provides 24 ports and 48 RapidIO Gen3 lanes with up to 600Gbps switching capacity.
Why It Matters
The successful bring-up strengthens China's domestic high-speed interconnect stack for AI servers, embedded computing, and heterogeneous accelerators. If validated in production systems, the chips could reduce dependence on external interconnect components and improve low-latency GPU-to-device data movement.
What To Do Next
Prototype a GPU Direct RDMA path with SR1820 and ST0420, then benchmark end-to-end bandwidth, tail latency, and CPU utilization against your current PCIe topology.
Who should care:Researchers & Academics
Key Points
- •SR1820 provides 24 ports and 48 RapidIO Gen3 lanes with up to 600Gbps switching capacity.
- •SR1820 supports 1.25–12.5Gbaud per lane, congestion detection, plug-and-play operation, and sub-100ns forwarding latency.
- •ST0420 performs hardware-based PCIe and RapidIO transaction conversion using an address-mapping engine, reducing processor involvement in bulk data transfers.
- •ST0420 provides four 12.5Gbaud RapidIO links, 50Gbps line-rate conversion, RDMA support, and latency below 200ns.
- •Together, the chips can enable GPU Direct RDMA links delivering over 40Gbps bandwidth with hundred-nanosecond-scale latency for AI parallel computing.
🧠 Deep Insight
Background and context from public sources — not the original article. 18 sources cited.
🔑 Enhanced Key Takeaways
- •Jingxin Microelectronics was established in 2020 as a fabless semiconductor company in Tianjin, China, originating from an industrialization project of the National Digital Switching System Engineering Technology Research Center Tianjin Center and the Binhai New Area Information Technology Innovation Center.
- •The company has successfully secured multiple rounds of venture capital funding, including a Series A financing in January 2023, raising over CNY 100.0M (approximately $14.7M), and a Series B stage in May 2024, securing an additional $13.9M.
- •RapidIO is an open standard, packet-switched interconnect technology specifically designed for high-performance embedded systems, facilitating chip-to-chip, board-to-board, and chassis-to-chassis communication.
- •The RapidIO Trade Association, responsible for standardizing the protocol, was founded around February 2000 with early members including Cisco Systems, Motorola (Freescale), and Xilinx, but has since ceased operations, with its assets now archived by VITA.
- •Jingxin Microelectronics had previously released the PRB0400 PCIe to SRIO bridge chip in October 2022, demonstrating a prior focus on integrating PCIe and RapidIO ecosystems for high-reliability, low-latency computing systems.
🛠️ Technical Deep Dive
- RapidIO employs a three-layer hierarchical architecture consisting of a logical layer, a transport layer, and a physical layer.
- The logical layer defines all protocols and packet formats, supporting input/output systems, message passing, and globally shared memory, including extensions for cache coherency and multiprocessing.
- The physical layer's electrical specifications are based on established industry standards such as XAUI for lower speeds, OIF CEI for intermediate speeds, and 10GBASE-KR Ethernet standards for higher lane rates.
- RapidIO's flow control mechanism allows control symbols to be embedded directly within data packets, which contributes to lower latency and higher throughput compared to PCI Express's Data Link Layer Packets (DLLPs) that can introduce more latency and jitter.
- The RapidIO protocol supports various lane speeds, ranging from 1.25 Gigabaud up to 25.3125 Gigabaud, and offers flexible port widths including 1, 2, 4, 8, and 16 lanes.
- While RapidIO 3.2 supports 12.5 Gbaud per lane and 50 Gbps per port, later versions like RapidIO 4.0 and 4.1 further increase performance to 25 Gbaud per lane and 100 Gbps per port.
- The ST0420 bridge chip's hardware-based PCIe and RapidIO transaction conversion, utilizing an address-mapping engine, significantly reduces the need for processor involvement in bulk data transfers, a key advantage for efficiency over software-dependent protocols.
🔮 Future ImplicationsAI analysis grounded in cited sources
China's domestic development of high-performance RapidIO chips will accelerate its self-sufficiency in critical computing infrastructure.
The successful power-on of these domestically developed chips by a Chinese fabless company, backed by substantial venture capital, directly supports China's strategic goal of reducing reliance on foreign semiconductor technology amidst global supply chain challenges and export controls.
The integration of RapidIO and PCIe ecosystems through bridge chips like ST0420 will enable more flexible and high-performance heterogeneous computing architectures for AI.
By efficiently converting transactions between these two prevalent protocols, the ST0420 allows GPUs (often PCIe-based) and other RapidIO-connected processing elements to communicate with low latency and high bandwidth, which is critical for advanced AI parallel computing.
The adoption of RapidIO in Chinese AI and data center infrastructure is likely to increase, potentially establishing it as a dominant interconnect standard in these specific domestic applications.
RapidIO's optimization for low-latency, peer-to-peer communication in embedded and high-performance computing aligns well with the demands of AI parallel computing and data centers, and China is actively promoting domestic technological adoption in these strategic sectors.
⏳ Timeline
2000-02
RapidIO Trade Association founded to standardize the RapidIO protocol.
2016-02
RapidIO specification revision 3.2, supported by Jingxin Microelectronics' new chips, was released.
2020
Jingxin Microelectronics Technology (Tianjin) Co., Ltd. established as a fabless semiconductor company.
2022-10
Jingxin Microelectronics releases its PRB0400 PCIe to SRIO bridge chip.
2023-01
Jingxin Microelectronics completes Series A funding round, raising over CNY 100.0M (~$14.7M).
2024-05
Jingxin Microelectronics reaches Series B funding stage, securing an additional $13.9M.
📎 Sources (18)
Factual claims are grounded in the sources below. Forward-looking analysis is AI-generated interpretation.
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