Automakers Shift to In-House Autonomous Driving Chip Development

๐กMajor automakers are moving to custom silicon, signaling a massive shift in the AI edge computing supply chain.
โก 30-Second TL;DR
What Changed
Five major automakers are now building proprietary silicon for autonomous driving.
Why It Matters
This shift threatens the market share of established chip vendors and forces a vertical integration trend in the automotive industry. It signals a move toward hardware-software co-design to optimize AI model inference on edge devices.
What To Do Next
Analyze the hardware-software integration requirements for your edge AI projects to determine if custom silicon or specialized accelerators are necessary for your performance targets.
Key Points
- โขFive major automakers are now building proprietary silicon for autonomous driving.
- โขIn-house development aims to challenge the dominance of traditional third-party chip suppliers.
- โขCompanies claim their custom chips meet or exceed the performance of commercially available solutions.
๐ง Deep Insight
Web-grounded analysis with 35 cited sources.
๐ Enhanced Key Takeaways
- โขAutomakers are pursuing in-house chip development to achieve significant cost reductions, with examples like BYD's Xuanji A3 being roughly one-third the hardware cost of Nvidia's Thor-based solutions, and Nio's Shenji NX9031 offering 10,000 yuan in cost optimization per vehicle.
- โขThis strategic shift is driven by the need for deep hardware-software integration to optimize performance and efficiency, as well as to leverage vast amounts of proprietary real-world driving data for rapid algorithm training and iteration.
- โขThe move also aims to mitigate supply chain disruptions and geopolitical risks, particularly for Chinese automakers facing restrictions on semiconductor exports.
- โขThe evolution of autonomous driving models towards end-to-end large models and "world models" necessitates specialized chip architectures that off-the-shelf solutions may not fully support.
๐ Competitor Analysisโธ Show
| Automaker/Supplier | Chip Name | Process Node | Peak TOPS (Single/Multi-chip) | Key Features/Architecture | Status/Availability |
|---|---|---|---|---|---|
| BYD | Xuanji A3 | 4nm | 700 TOPS (single), >2100 TOPS (3-chip) | 16-core CPU, 273 GB/s bandwidth, 420k DMIPS, lowest power consumption (20% less), ASIL-D safety, underpins God's Eye system | Mass production (May 2026) |
| NIO | Shenji NX9031 | 5nm | 1028 TOPS (single), >2000 TOPS (dual) | 50+ billion transistors, 32-core CPU, LPDDR5X, 6.5 Gpixel/s ISP, ASIL-D safety, comparable to 4x Nvidia Orin X | In use in ET9, ES6, EC6 (late 2023/early 2024). Licensing tech to others. |
| XPeng | Turing AI chip | Not specified (purpose-built) | 700-750 TOPS (single), 2250 TOPS (3-chip) | 40-core processor, supports 30B parameters, 2 proprietary neural cores, 20% better utilization, integrated 2 NPU, domain-specific architecture | Nearing mass production (April 2025), debuted in G7 SUV (June 2025) |
| Li Auto | M100 (Mahe 100) | 5nm automotive-grade | 1280 TOPS (single), 2560 TOPS (dual) | AI inference chip, data-flow architecture, 3x performance for matrix multiplication, designed for VLA model | Expected deployment in 2026 |
| Tesla | FSD Chip (HW3) | 14nm | 144 TOPS | 6 billion transistors, 2x 36 TOPS neural network accelerators, vision-only approach | Introduced April 2019 |
| Tesla | FSD Computer 2 (HW4) | Not specified (rumored 3nm for next-gen CPU) | 3-8x HW3 (estimated 432-1152 TOPS) | 16GB RAM, 256GB storage, upgraded GPS, radar interface, symmetrical dual backup design | Shipping since Jan 2023 |
| NVIDIA | DRIVE Orin | 7nm | 200 TOPS | Ampere architecture, AI acceleration, scalable L2+ to L5 | Available for 2022 model year |
| NVIDIA | DRIVE Thor | Not specified | 700 TOPS | High-performance automotive chip | Facing delays |
| Qualcomm | Snapdragon Ride Elite | Not specified | Not specified (focus on balanced performance) | Custom Oryon CPU, 12x faster Hexagon NPU, sensor fusion, real-time decision-making | Supports ADAS/AD functionalities |
| Qualcomm | Snapdragon Ride Flex SoC | Not specified | Scalable from entry to L4 | Unified architecture for mixed-criticality workloads (cockpit, ADAS, AD on single chip), cost savings | Sampling in 2025 |
๐ ๏ธ Technical Deep Dive
- BYD Xuanji A3: 4nm process, 16-core CPU, 273 GB/s bandwidth, 420,000 DMIPS of processing performance, meets ASIL-D functional safety rating, and offers 20% lower power consumption per unit of compute compared to similar products.
- NIO Shenji NX9031: Built on a 5nm process with over 50 billion transistors, features LPDDR5X memory, a 32-core CPU (with a mix of large and small cores), a high-dynamic range processor (ISP) with a pixel processing speed of 6.5 Gpixel/s, and supports ASIL-D safety.
- XPeng Turing AI chip: Features a 40-core processor, supports models with up to 30 billion parameters, is built around two proprietary neural cores, integrates two Neural Processing Units (NPUs), and utilizes a domain-specific architecture for neural networks, along with two independent image ISPs.
- Li Auto M100 (Mahe 100): Uses a 5nm automotive-grade process and adopts a data-flow architecture, which is data-driven with direct data transmission between computing units to reduce data transfer loss, and is optimized for Visual-Language-Action (VLA) models.
- Tesla FSD Chip (HW3): Manufactured using 14nm technology, contains 6 billion transistors, and comprises two independent systems, each with a processor featuring 12 A72 cores, a GPU, and a Neural Network processor, with two neural network accelerators per chip, each capable of 36 TOPS.
- Tesla FSD Computer 2 (HW4): Features 16 GB of RAM and 256 GB of storage, an upgraded triple-band GPS antenna module (adding the L5 frequency), a millimeter wave radar interface, and a symmetrical motherboard design with dual backup.
๐ฎ Future ImplicationsAI analysis grounded in cited sources
โณ Timeline
๐ Sources (35)
Factual claims are grounded in the sources below. Forward-looking analysis is AI-generated interpretation.
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