๐งTom's HardwareโขFreshcollected in 1m
AI Optical Interconnects Set for 10x Market Growth
#data-centers#bandwidth#networkingsilicon-photonics-optical-interconnectscicsilicon photonicsco-packaged optics
๐กAI clusters may soon depend on a $144 billion optical interconnect market dominated by Silicon photonics.
โก 30-Second TL;DR
What Changed
The market is forecast to expand from $13.7 billion in 2024 to $144.4 billion by 2030.
Why It Matters
Rapid growth in optical interconnects could reshape the networking architectures used for large-scale AI training and inference. AI infrastructure teams may need to evaluate optical bandwidth, power efficiency, and integration strategies earlier in their cluster planning.
What To Do Next
Benchmark optical-network bandwidth and power requirements for your next AI cluster, including whether co-packaged optics could reduce interconnect bottlenecks.
Who should care:Enterprise & Security Teams
Key Points
- โขThe market is forecast to expand from $13.7 billion in 2024 to $144.4 billion by 2030.
- โขSilicon photonics is projected to account for 63.7% of total market revenue.
- โขCo-packaged optics is identified as a major driver of future data center adoption.
- โขThe forecast implies more than ten-fold growth within six years.
๐ง Deep Insight
AI-generated analysis for this event.
๐ Enhanced Key Takeaways
- โขThe surge in optical interconnect demand is primarily driven by the transition from pluggable transceivers to co-packaged optics (CPO) to overcome the 'bandwidth wall' in AI clusters.
- โขMajor hyperscalers like NVIDIA, Meta, and Microsoft are actively integrating silicon photonics to reduce power consumption per bit, which is critical for scaling GPU clusters beyond 100,000 units.
- โขThe shift toward optical I/O is enabling disaggregated data center architectures, allowing memory and compute resources to be physically separated while maintaining low-latency communication.
- โขThermal management remains a significant technical hurdle for CPO, as placing lasers and optical engines in close proximity to high-heat-generating ASICs requires advanced packaging solutions.
- โขFoundry capacity for silicon photonics is expanding rapidly, with major players like TSMC, GlobalFoundries, and Intel investing in specialized manufacturing processes to support high-volume production.
๐ Competitor Analysisโธ Show
| Technology Approach | Key Players | Primary Advantage | Primary Challenge |
|---|---|---|---|
| Pluggable Optics | Coherent, Lumentum, InnoLight | Mature ecosystem, field-replaceable | Power/density limits at 800G+ |
| Co-Packaged Optics (CPO) | NVIDIA, Broadcom, Intel | Lowest power/latency, high density | Complex thermal/repairability |
| Optical I/O Chiplets | Ayar Labs, Lightmatter | Disaggregation, extreme bandwidth | Integration with existing CMOS |
| Silicon Photonics | GlobalFoundries, TSMC | Scalable manufacturing | Laser integration/reliability |
๐ ๏ธ Technical Deep Dive
- Silicon photonics utilizes standard CMOS fabrication processes to integrate optical components like modulators, waveguides, and photodetectors on silicon wafers.
- Co-packaged optics (CPO) moves the optical engine from the front panel to the substrate, significantly reducing the electrical trace length between the switch/GPU and the optical module.
- Optical I/O chiplets leverage wavelength division multiplexing (WDM) to increase data throughput over a single fiber by transmitting multiple data streams on different wavelengths.
- Advanced packaging techniques such as 2.5D and 3D stacking are essential for connecting the optical engine to the compute die with minimal signal loss.
- The transition to 1.6T and 3.2T pluggable and CPO modules is driving the adoption of higher-order modulation formats like PAM4 and potentially coherent optics for shorter reaches.
๐ฎ Future ImplicationsAI analysis grounded in cited sources
Power consumption per gigabit will drop by over 50% by 2028.
The elimination of power-hungry electrical retimers and the reduction of trace lengths through CPO significantly improve energy efficiency in high-density AI fabrics.
CPO will capture more than 30% of the high-end AI switch market by 2029.
As AI cluster sizes exceed the physical limits of copper and traditional pluggable optics, hyperscalers are increasingly mandating CPO for next-generation infrastructure.
โณ Timeline
2021-03
OIF launches the Co-Packaged Optics (CPO) Framework project to standardize next-gen interfaces.
2022-09
NVIDIA introduces the NVLink Switch System, highlighting the need for high-bandwidth, low-latency interconnects.
2023-11
Ayar Labs demonstrates 4Tbps optical I/O chiplet technology, marking a milestone for disaggregated compute.
2024-06
Major industry players finalize specifications for 800G and 1.6T optical interconnect standards.
2025-05
First large-scale deployments of CPO-enabled AI switches begin in hyperscale data centers.
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Original source: Tom's Hardware โ