🔥36氪•Freshcollected in 21m
TSMC June Revenue Grows 67.9% Year-over-Year
💡TSMC's revenue is a key leading indicator for the global AI hardware supply chain and chip availability.
⚡ 30-Second TL;DR
What Changed
June revenue reached 442.68 billion TWD
Why It Matters
Strong growth indicates sustained high demand for AI-related semiconductor manufacturing and advanced process nodes.
What To Do Next
Analyze TSMC's capacity reports to forecast supply chain availability for your hardware-dependent AI projects.
Who should care:Developers & AI Engineers
Key Points
- •June revenue reached 442.68 billion TWD
- •Year-over-year growth of 67.9%
- •H1 2026 total revenue grew by 35.6%
🧠 Deep Insight
AI-generated analysis for this event.
🔑 Enhanced Key Takeaways
- •The surge in revenue is primarily attributed to the aggressive ramp-up of 2nm (N2) process technology production and sustained high demand for AI-accelerator chips from major hyperscalers.
- •TSMC's capacity utilization rates for advanced nodes (3nm and 5nm) have reached near-maximum levels, driven by the integration of CoWoS (Chip-on-Wafer-on-Substrate) packaging solutions.
- •The company has increased its capital expenditure (CapEx) guidance for 2026 to support the expansion of overseas fabs in Arizona and Japan, aiming to diversify geopolitical supply chain risks.
- •Average Selling Price (ASP) per wafer has seen a notable uptick as TSMC shifts its product mix further toward high-margin AI and high-performance computing (HPC) silicon.
- •The revenue growth reflects a broader industry recovery in the smartphone and automotive sectors, which have begun to stabilize after the inventory correction cycles of 2024-2025.
📊 Competitor Analysis▸ Show
| Feature/Metric | TSMC | Samsung Foundry | Intel Foundry |
|---|---|---|---|
| Leading Node | 2nm (N2) | 2nm (SF2) | 18A |
| Packaging | CoWoS / SoIC | I-Cube / X-Cube | Foveros |
| Market Position | Dominant (Foundry) | Challenger | Emerging |
| AI Focus | High (NVIDIA/AMD) | Moderate | High (Internal/External) |
🛠️ Technical Deep Dive
- N2 (2nm) Process: Utilizes nanosheet transistor architecture (GAA) to provide significant power, performance, and area (PPA) improvements over FinFET.
- CoWoS-R/L/S: Advanced 2.5D/3D packaging technologies enabling high-bandwidth memory (HBM) integration with logic dies for AI workloads.
- EUV Lithography: High-NA EUV scanners are being deployed to support the scaling requirements of sub-2nm nodes.
- Backside Power Delivery: Implementation of advanced power delivery networks to reduce IR drop and improve signal integrity in high-performance chips.
🔮 Future ImplicationsAI analysis grounded in cited sources
TSMC will maintain a global foundry market share exceeding 60% through 2027.
The company's lead in advanced packaging and node maturity creates a high barrier to entry that competitors are struggling to overcome.
Operating margins will expand in Q4 2026 due to the full-scale commercialization of N2 technology.
As yields improve on the new node, the initial high costs of R&D and ramp-up will be offset by premium pricing for AI-focused clients.
⏳ Timeline
2025-01
TSMC announces record-breaking annual revenue for 2024, signaling strong recovery.
2025-07
TSMC begins pilot production of 2nm (N2) process technology.
2026-01
TSMC reports strong Q4 2025 earnings, driven by AI chip demand.
2026-04
TSMC confirms expansion of advanced packaging capacity to meet CoWoS demand.
2026-07
TSMC reports June 2026 revenue growth of 67.9% year-over-year.
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Original source: 36氪 ↗