NVIDIA GTC: Focus on LPU and Supply Chain Leaders

🔑 Enhanced Key Takeaways

• •NVIDIA entered a licensing agreement with Groq in December 2025, enabling integration of Groq's LPU technology into NVIDIA's LPX racks rather than a full acquisition[1][3][4].
• •LPX racks will scale from 64 LPUs (as 32 RealScale ASIC tiles) in initial versions to 256 LPUs per rack at GTC 2026, using 52-layer M9 Q-glass PCBs for enhanced inference performance[1].
• •Groq LPUs leverage hundreds of megabytes of on-chip SRAM with 80 TB/s bandwidth for deterministic, low-latency decode, demonstrated by generating 10,000 tokens in two seconds[1][4].
• •GTC 2026 is scheduled for March 16-19 in San Jose, with Jensen Huang's keynote promising 'several new chips the world has never seen,' including potential Feynman architecture for agentic AI[2][3][5].

🛠️ Technical Deep Dive

• •LPUs use fixed dataflow architecture similar to systolic arrays in TPUs, enabling full 80 TB/s SRAM bandwidth utilization without cache variability for sequential decode tasks[4].
• •Prefill phase (compute-bound, parallel token processing to build KV cache) is targeted by Rubin CPX using GDDR7 memory, as bandwidth is not the bottleneck[4].
• •Decode phase (memory-bound, sequential token generation) benefits from LPU's deterministic network and on-chip SRAM, outperforming general-purpose GPUs in low-batch, real-time inference[1][4].
• •Initial LPX racks integrate 64 LPUs as 32 RealScale ASIC tiles, supporting millisecond-latency for small batches in long-context and real-time audio/video workloads[1].

🔮 Future ImplicationsAI analysis grounded in cited sources

⏳ Timeline