🔥36氪•Recentcollected in 14m
Nomura: Concerns over 'compute oversupply' are likely overstated
💡Crucial market insight on why the AI compute supply crunch is likely to persist.
⚡ 30-Second TL;DR
What Changed
AI demand for HBM is causing supply constraints in standard memory
Why It Matters
This suggests that the AI infrastructure boom, particularly in memory, will likely remain supported by supply-demand imbalances for the foreseeable future.
What To Do Next
Adjust supply chain forecasting models to account for extended lead times in memory procurement for AI clusters.
Who should care:Developers & AI Engineers
Key Points
- •AI demand for HBM is causing supply constraints in standard memory
- •Long semiconductor construction cycles prevent rapid supply spikes
- •Market concerns regarding compute oversupply are currently overstated
🧠 Deep Insight
AI-generated analysis for this event.
🔑 Enhanced Key Takeaways
- •Nomura's analysis highlights that HBM3e and future HBM4 iterations consume significantly more wafer capacity than standard DDR5, effectively reducing the total addressable supply for commodity memory markets.
- •The 'capital intensity' of AI-focused fabs has shifted, with major manufacturers prioritizing high-margin HBM production over legacy nodes, creating a structural supply floor for standard DRAM prices.
- •Industry data indicates that while AI server shipments are growing, the actual utilization rates of deployed compute clusters remain below peak capacity, suggesting that 'oversupply' fears stem from deployment lag rather than lack of demand.
- •Semiconductor equipment lead times for advanced lithography tools (EUV) remain extended, acting as a natural barrier to entry that prevents new market entrants from rapidly flooding the supply chain.
- •Nomura identifies that memory manufacturers are exercising 'supply discipline' by converting existing capacity to HBM rather than building massive new greenfield fabs, which mitigates the risk of a traditional boom-bust cycle.
🛠️ Technical Deep Dive
- HBM (High Bandwidth Memory) utilizes a 3D-stacked architecture with Through-Silicon Vias (TSVs) to connect DRAM dies, which requires significantly more complex packaging processes compared to standard 2D DRAM.
- The shift toward HBM3e and HBM4 involves increased die counts per stack and higher I/O speeds, which necessitates advanced thermal management and specialized interposer technology.
- Wafer utilization for HBM is less efficient than standard DRAM because the complex stacking and testing processes result in lower overall yield per wafer, effectively tightening supply for non-AI memory products.
🔮 Future ImplicationsAI analysis grounded in cited sources
Standard DRAM prices will remain elevated through 2027.
The structural diversion of wafer capacity toward HBM production limits the supply elasticity of commodity memory, keeping prices high despite fluctuating consumer electronics demand.
Memory manufacturers will prioritize HBM4 yield improvements over capacity expansion.
Given the high capital expenditure required for new fabs, firms are incentivized to maximize revenue per wafer through advanced packaging rather than volume-based commodity production.
⏳ Timeline
2023-05
Nomura initiates coverage on global memory sector with focus on AI-driven supply shifts.
2024-02
Nomura publishes research note highlighting the impact of HBM production on standard DRAM availability.
2025-09
Nomura analysts revise memory supply forecasts, citing persistent HBM capacity constraints.
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Original source: 36氪 ↗