⚛️量子位•Freshcollected in 61m
Intel unveils three pillars for future chip innovation
💡Intel's roadmap for next-gen AI hardware: CFET and GaN integration explained.
⚡ 30-Second TL;DR
What Changed
Introduction of CFET architecture for density
Why It Matters
These advancements are critical for the next generation of AI accelerators, enabling higher power efficiency and transistor density for massive workloads.
What To Do Next
Monitor Intel's foundry roadmap updates to align your hardware-dependent AI deployment strategies with these upcoming process nodes.
Who should care:Researchers & Academics
🧠 Deep Insight
Web-grounded analysis with 20 cited sources.
🔑 Enhanced Key Takeaways
- •Intel has demonstrated monolithic CFET inverters with vertically stacked NMOS and PMOS devices at a 45nm gate pitch, advancing transistor scaling beyond Gate-All-Around (GAA) architectures.
- •Intel Foundry achieved 300mm monolithic integration of gallium nitride (GaN) power devices with silicon logic, including a ~1,000 gate digital control block, enabling efficient, large-scale digital control alongside high-performance power devices on a single chip and reducing system complexity.
- •Intel's subtractive ruthenium interconnect technology, combined with airgap integration, has shown up to a 35% capacitance reduction and measurable frequency gains compared to copper, positioning ruthenium as a key alternative metallization material for future process nodes where copper's effectiveness diminishes below 2nm line widths.
🛠️ Technical Deep Dive
- CFET (Complementary FET): This architecture involves vertically stacking n-type (NMOS) and p-type (PMOS) transistors, a departure from traditional side-by-side configurations, to increase device density. Intel demonstrated monolithic CFET inverters at a 45nm gate pitch. Two primary integration schemes exist: monolithic (where NFET and PFET are grown together, offering better performance and lower cost but requiring extremely high aspect ratio etching) and sequential (allowing more flexibility in channel materials).
- Gallium Nitride (GaN) on Silicon: Intel demonstrated 300mm monolithic integration of GaN power devices with silicon logic. This includes a ~1,000 gate digital control block on the same chip. Intel Foundry has also developed an ultra-thin GaN chiplet with a silicon base thickness of just 19 micrometers, integrating GaN transistors with on-die silicon-based digital control circuits using a unified manufacturing process. This integration, operating on a 30nm process, exhibits stable current carrying, very low power loss, and the ability to block voltages up to 78V without leakage, achieving switching times of 33 picoseconds.
- Ruthenium Interconnects: Intel's approach involves subtractive ruthenium with airgap integration. Ruthenium is being explored as a replacement for copper and aluminum in future processes, particularly for sub-2nm nodes where copper's resistivity advantages diminish. Key advantages of ruthenium include lower diffusion into surrounding oxides, potentially eliminating the need for barrier layers used with copper, and compatibility with subtractive etching. This allows for a greater cross-sectional area for current flow. The subtractive ruthenium process with airgaps can provide up to 25% capacitance reduction at sub-25nm pitches.
🔮 Future ImplicationsAI analysis grounded in cited sources
These innovations will enable the continuation of Moore's Law by pushing transistor density and performance beyond current limitations.
CFET's vertical stacking and GaN's integration with silicon logic offer new avenues for increasing transistor density and functional integration, while ruthenium addresses interconnect scaling challenges critical for future nodes.
The integration of GaN with silicon logic will lead to more efficient and compact power delivery solutions for high-performance computing and AI.
Combining power devices and digital control on a single chip reduces system complexity, interconnect losses, and improves overall power efficiency, which is crucial for demanding applications like data centers and electric vehicles.
The adoption of ruthenium interconnects will significantly improve signal integrity and reduce power consumption in advanced chips.
Ruthenium's superior electrical properties at smaller dimensions, including lower capacitance and the ability to operate without resistive barrier layers, will enhance chip performance and energy efficiency.
⏳ Timeline
1993
Gallium Nitride (GaN) research began at UCSB, though initially considered 'useless' as a semiconductor.
1997
Copper interconnects were introduced, replacing tungsten/aluminum schemes.
2009
Efficient Power Conversion (EPC) unveiled the first enhancement-mode GaN on silicon wafers for power MOSFET replacements.
2018
IMEC proposed the Complementary-FET (CFET) concept.
2023-12
Intel demonstrated the vertical stacking of CFETs at a 60nm gate pitch, combined with backside power and direct backside contacts.
2026-06
Intel demonstrated monolithic CFET inverters at a 45nm gate pitch, 300mm monolithic GaN+Si integration, and subtractive ruthenium interconnects with airgap integration at the VLSI Symposium.
📎 Sources (20)
Factual claims are grounded in the sources below. Forward-looking analysis is AI-generated interpretation.
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