Google Partners with Samsung to Ease AI Chip Shortage

🔑 Enhanced Key Takeaways

•Google is implementing a 'split manufacturing strategy' for its upcoming 10th-generation Tensor Processing Unit (TPU), codenamed 'Icefish,' where TSMC will produce the primary compute component using its 1.4-nanometer process, and Samsung will manufacture a separate memory-interface component (I/O die) using its 2-nanometer process.
•Beyond Samsung, Google has been actively diversifying its AI chip supply chain, collaborating with design partners such as Broadcom, MediaTek, and Marvell for various custom chips, including inference-optimized TPUs and Memory Processing Units (MPUs).
•The global AI chip shortage extends beyond just processing units to include High Bandwidth Memory (HBM), which is critical for training large AI models, leading to supply constraints and increased prices across the semiconductor industry.
•Google is also reportedly in talks with Intel to manufacture more than three million TPUs by 2028, further expanding its manufacturing partnerships beyond TSMC and the newly reported Samsung collaboration.

🛠️ Technical Deep Dive

TPUs are Application-Specific Integrated Circuits (ASICs) developed by Google for neural network machine learning, specifically optimized for matrix multiplication and tensor operations.
The architecture features TensorCores, each containing one or more Matrix-Multiply Units (MXUs), a vector unit, and a scalar unit. MXUs are systolic arrays, with earlier versions having 128x128 multiply-accumulators and later versions (v6e, v7x) having 256x256.
TPUs utilize bfloat16 inputs for multiplies and perform accumulations in FP32 format.
Inter-chip communication is crucial, with TPUs arranged in 3D mesh or 3D torus topologies, scaling up to 9,216 chips in a superpod for the Ironwood (TPU v7) generation, delivering 42.5 FP8 exaflops.
High Bandwidth Memory (HBM) is a key component, with Ironwood (TPU v7) featuring 192GB of HBM3e memory per chip with 7.2-7.4 TB/s bandwidth.
The upcoming 10th-generation TPU, 'Icefish,' will reportedly use TSMC's 1.4nm process for the main compute and Samsung's 2nm process for the memory I/O die, leveraging Samsung's expertise in HBM integration and advanced packaging.
Google's 8th generation TPUs (TPU 8t for training and TPU 8i for inference) represent a bifurcation of architecture, optimized for specific workloads, and are hosted on Google's custom Arm-based Axion CPUs.

🔮 Future ImplicationsAI analysis grounded in cited sources

Google will achieve greater supply chain resilience and cost efficiency in AI chip production.

Diversifying manufacturing partners and utilizing advanced process nodes from both TSMC and Samsung reduces reliance on a single vendor and leverages competitive pricing and specialized expertise.

Samsung Foundry will significantly strengthen its position in the advanced AI chip manufacturing market.

Securing a contract for a critical component of Google's next-generation TPU, especially using its 2nm process, validates Samsung's advanced foundry capabilities and attracts other major AI chip customers.

The trend of hyperscalers designing custom AI silicon and adopting split manufacturing strategies will accelerate.

The intense competition for AI compute and the limitations of single-foundry reliance will push more large tech companies to pursue similar multi-partner design and manufacturing approaches.

⏳ Timeline

2013

Google establishes custom silicon development capabilities, initiating the TPU project.

2015

Google deploys the first-generation TPU (TPU v1) internally for inference workloads.

2017

Google announces the second-generation TPU (TPU v2), capable of both training and inference.

2018

Google makes TPUs available for third-party use through its cloud infrastructure.

2021

Google unveils the fourth-generation TPU (TPU v4), introducing SparseCores and optical circuit switching.

2025

Google launches Ironwood (TPU v7), optimized for inference at scale.

2026-04

Google announces its eighth generation TPUs, TPU 8t (training) and TPU 8i (inference), marking a bifurcation in architecture.

2026-06

Reports emerge of Google's talks with Samsung to manufacture a memory-interface component for its 10th-generation TPU, 'Icefish,' with mass production targeted for 2028.