BiCS10 Sets New 3D NAND Density Record
💡A denser NAND design could make AI datasets and model checkpoints cheaper to store.
⚡ 30-Second TL;DR
What Changed
The BiCS10 device contains 332 active 3D NAND layers.
Why It Matters
Higher-density QLC NAND could reduce the footprint and cost of storage used for AI datasets, checkpoints, and inference caches. However, production availability, endurance, and real-world latency will determine its suitability for demanding AI workloads.
What To Do Next
Benchmark your AI checkpoint and dataset workloads on high-density QLC SSDs once BiCS10-based products become available, measuring endurance and read latency alongside cost per terabyte.
Key Points
- •The BiCS10 device contains 332 active 3D NAND layers.
- •Its areal density exceeds 37 Gbit/mm², described as a record.
- •The interface reaches up to 4,800 MT/s for higher flash data throughput.
🧠 Deep Insight
AI-generated analysis for this event.
🔑 Enhanced Key Takeaways
- •BiCS10 utilizes a multi-deck architecture, likely employing a 4-deck or 5-deck stacking process to achieve the 332-layer height while maintaining structural integrity.
- •The 4,800 MT/s interface speed is achieved through the adoption of the ONFI 5.1 or a similar high-speed NAND interface standard, significantly reducing latency compared to previous generations.
- •Kioxia and Western Digital (SanDisk) have optimized the channel hole etching process to maintain high aspect ratios, which is critical for scaling beyond 300 layers.
- •The QLC (Quad-Level Cell) implementation in BiCS10 incorporates advanced error correction code (ECC) engines to compensate for the reduced voltage margins inherent in 4-bit-per-cell storage.
- •This generation marks a shift toward 'CMOS-under-Array' (CUA) 2.0 or 3.0 architectures, where peripheral circuitry is further miniaturized to maximize the silicon area dedicated to memory cells.
📊 Competitor Analysis▸ Show
| Feature | BiCS10 (Kioxia/SanDisk) | Samsung V-NAND (Gen 10+) | Micron G9/G10 NAND |
|---|---|---|---|
| Layer Count | 332 | ~300-350 (Est.) | ~300+ (Est.) |
| Areal Density | >37 Gbit/mm² | Competitive | Competitive |
| Interface Speed | 4,800 MT/s | 4,200-4,800 MT/s | 4,000-4,800 MT/s |
| Cell Type | QLC | QLC/TLC | QLC/TLC |
🛠️ Technical Deep Dive
- Architecture: Multi-deck vertical stacking utilizing advanced channel hole etching to manage aspect ratio challenges.
- Interface: High-speed I/O supporting 4,800 MT/s, likely leveraging ONFI 5.1 specifications.
- Density Optimization: Enhanced CMOS-under-Array (CUA) design to minimize peripheral footprint and maximize active cell area.
- Reliability: Integration of sophisticated ECC and signal processing algorithms to manage the tight voltage thresholds of QLC storage at high layer counts.
🔮 Future ImplicationsAI analysis grounded in cited sources
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Original source: Tom's Hardware ↗