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Ascend 910C Completes Training of 1.6 Trillion Parameter Model
๐กFirst major proof that domestic hardware can handle 1T+ parameter model training, signaling a shift in AI infrastructure
โก 30-Second TL;DR
What Changed
Ascend 910C successfully trained a 1.6 trillion parameter model
Why It Matters
This breakthrough suggests that domestic Chinese hardware is becoming increasingly capable of handling frontier-scale model training, potentially reducing reliance on imported GPUs.
What To Do Next
Evaluate the Ascend 910C cluster performance metrics if you are building large-scale models for the Chinese market.
Who should care:Researchers & Academics
Key Points
- โขAscend 910C successfully trained a 1.6 trillion parameter model
- โขCollaboration between Huawei, Shenzhen Hetao College, and local research institutes
- โขDemonstrates viability of domestic hardware for large-scale model training
๐ง Deep Insight
Web-grounded analysis with 21 cited sources.
๐ Enhanced Key Takeaways
- โขThe 1.6 trillion parameter model successfully post-trained on the Ascend 910C is identified as DeepSeek-V4-Pro.
- โขThe training utilized a cluster of over 1,000 Huawei Ascend 910C chips.
- โขThe project achieved a Model Floating-point Utilization (MFU) exceeding 30% and a 14% improvement in key operator efficiency, with no system failures over 1,500+ training steps.
- โขThis milestone specifically involved 'full-parameter post-training,' which focuses on supervised fine-tuning (SFT) and reinforcement learning (RL) rather than pre-training from scratch.
- โขThe collaborative effort included Shenzhen Hetao College, Harbin Institute of Technology (Shenzhen), Shenzhen Institute of Big Data, and Huawei-related teams.
๐ Competitor Analysisโธ Show
Competitor Analysis: Huawei Ascend 910C vs. Key AI Accelerators
| Feature/Metric | Huawei Ascend 910C | Nvidia H100 (Hopper) | AMD Instinct MI300X | Intel Gaudi 3 |
|---|---|---|---|---|
| Process Node | SMIC 7nm (N+2) | TSMC 4nm (4NP) | TSMC 5nm + 6nm (chiplet) | TSMC 5nm |
| Architecture | Dual-die packaging (two Ascend 910B chips) | Hopper (monolithic) | CDNA 3 (chiplet) | Habana Labs custom |
| FP16 Performance | ~800 TFLOPS | ~1,979 TFLOPS (dense) | ~1,308 TFLOPS (dense) | ~1,835 TFLOPS (dense) |
| Memory Bandwidth | 3.2 TB/s | 3.35 TB/s | 5.3 TB/s | 3.7 TB/s |
| TDP | 550 W | 700 W | 750 W | 900 W |
| Relative Performance (vs. H100) | 60-80% (FP16) | 100% | ~75-80% (for training GPT-style models) | Not directly comparable, but strong training efficiency |
| Estimated Cost (per unit/solution) | 60-70% lower than H100 solutions | ~$25,000 - $30,000 (H100) | ~$8,000 - $10,000 (MI300X) | Not readily available |
| Interconnect Bandwidth | 512 GB/s bidirectional mesh (across cores) | 900 GB/s (NVLink) | 800 GB/s (Infinity Fabric) | 9.6 TB/s (Ethernet-based) |
| Ecosystem Maturity | Developing (CANN, MindSpore) | Mature (CUDA, extensive libraries) | Growing (ROCm) | Developing (Habana SynapseAI) |
๐ ๏ธ Technical Deep Dive
- Architecture: The Ascend 910C utilizes a dual-die packaging design, effectively integrating two Ascend 910B chips onto an organic substrate.
- Manufacturing Process: It is fabricated using SMIC's 7nm (N+2) process technology.
- Transistor Count: The chip contains approximately 53 billion transistors.
- Peak Throughput: The Ascend 910C offers a peak throughput of 800 TFLOPS for FP16 (BF16/FP16) operations. It also supports 100 TFLOPS for FP32 and 800 TOPS for INT8 tensor operations.
- Memory Bandwidth: It features a memory bandwidth of 3.2 TB/s.
- Thermal Design Power (TDP): The chip has a TDP of 550 W.
- AI Cores: Each Ascend 910C NPU integrates multiple AI cores, with some sources indicating 8 cores per chip (or 32+ in dual-die variants), each featuring a 256x256 Tensor (Cube) array.
- On-Chip Memory Hierarchy: Includes L1 Buffer (128โ512 KB/core), a 32 MB shared L2 Cache with 1 TB/s aggregate internal bandwidth, specialized L0A/L0B/L0C buffers for cube operand staging, and a 196 KB/core Unified Buffer (UB) for low-latency tile operations.
- Interconnects: Features a 512 GB/s bidirectional mesh network for inter-AI core communication, PCIe 4.0 ร16 (64 GB/s) for host-NPU communication, and supports Distributed HCCL (Huawei Collective Communication Library) over PCIe or TCP for multi-node clusters.
- Software Stack: The core software stack is the CANN (Compute Architecture for Neural Networks) framework, which provides low-level tools, runtime libraries, and over 1,000 operators. It includes AscendCL for unified programming and integrates with MindSpore, Huawei's PyTorch-like framework.
๐ฎ Future ImplicationsAI analysis grounded in cited sources
China's domestic AI hardware ecosystem will continue to reduce reliance on foreign suppliers for large-scale AI model training.
The successful full-parameter post-training of a 1.6 trillion parameter model on the Ascend 910C demonstrates the technical feasibility and growing maturity of domestic chips for demanding AI tasks, moving beyond just inference.
Huawei's Ascend series will become a more viable and cost-effective alternative to Nvidia for Chinese customers.
The Ascend 910C offers competitive performance (60-80% of H100) at a significantly lower cost, making it an attractive option, especially given US restrictions on Nvidia.
Future Ascend chips (950, 960, 970 series) will further close the performance gap with leading international competitors.
Huawei has outlined an aggressive roadmap for its Ascend chips, with plans to double compute power, memory, and interconnect capacity in subsequent generations, and introduce new low-precision formats.
โณ Timeline
2018-10
Huawei announces Ascend 910 and Ascend 310 AI chips.
2019-08
Huawei officially launches the Ascend 910.
2020
Huawei is added to the US Entity List, leading to increased reliance on domestic manufacturing partners like SMIC.
2025-09
Huawei unveils a three-year roadmap for its next-generation Ascend AI chips, including the 950, 960, and 970 series.
2026-01
The Ascend 950PR, optimized for prefill inference and recommendation, is expected to be released.
2026-06
Ascend 910C completes full-parameter post-training of the 1.6 trillion parameter DeepSeek-V4-Pro model.
๐ Sources (21)
Factual claims are grounded in the sources below. Forward-looking analysis is AI-generated interpretation.
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Original source: Pandaily โ