Apple A20 Pro May Adopt 96-bit LPDDR6 Memory

🔑 Enhanced Key Takeaways

• •The transition to a 96-bit bus is facilitated by the adoption of LPDDR6, which supports higher pin speeds (up to 10.667 Gbps or higher) compared to LPDDR5X, significantly increasing total memory bandwidth.
• •Industry analysts suggest the 96-bit configuration is a 'middle-ground' architecture, avoiding the extreme complexity and power draw of a 128-bit bus while still providing a ~50% bandwidth increase over the traditional 64-bit interface.
• •Apple's move is driven by the increasing memory bandwidth requirements of 'Apple Intelligence' features, specifically the need to keep larger LLM parameter weights in active memory to reduce latency during token generation.
• •The shift necessitates a redesign of the A-series memory controller (NOC - Network on Chip) to handle the non-standard bus width, which may impact die size and thermal management strategies.
• •Supply chain reports indicate that LPDDR6 pricing remains at a premium, forcing Apple to optimize the A20 Pro's silicon area to offset the increased cost of the memory subsystem within the overall Bill of Materials (BOM).

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