來源SCMP Technology•較早收集於 7m
Empyrean Technology 支持華為的新晶片縮放方法論
💡了解中國 EDA 生態系統如何演進以繞過美國制裁，並維持 AI 晶片的生產能力。
⚡ 30 秒速覽
有什麼變化
Empyrean Technology 發布了用於晶片設計物理驗證的 Argus 工具。
為什麼重要
本土 EDA 工具與華為架構的整合，可能加速國產 AI 晶片的開發，進而減輕美國制裁對高效能運算硬體的影響。
下一步行動
監控 Argus 與 Cadence 或 Synopsys 工具的效能基準測試，以評估非美國 EDA 技術堆疊在 AI 硬體開發中的可行性。
誰應關注：Developers & AI Engineers
關鍵要點
- •Empyrean Technology 發布了用於晶片設計物理驗證的 Argus 工具。
- •該工具支援華為旨在繞過先進製程限制的新型縮放法則。
- •中國企業正試圖減少對美國 EDA 軟體供應商的依賴。
🧠 深度解析
背景與延伸：來自公開資料，非原文內容。引用 17 個來源。
🔑 增強重點摘要
- •Huawei's new chip scaling methodology, dubbed the "Tau Scaling Law," focuses on optimizing the time it takes for signals and data to move through chips and computing systems, rather than solely relying on transistor miniaturization, which is approaching physical limits.
- •The "Tau Scaling Law" is implemented through a related architecture called "LogicFolding," which involves vertically stacking logic circuits into multiple layers using ultra-precise hybrid bonding to shorten wiring paths and improve performance and energy efficiency.
- •Huawei aims to achieve a transistor density equivalent to 1.4-nanometer processes by 2031 using its new scaling approach, an ambitious target that seeks to circumvent limitations imposed by US sanctions on advanced lithography tools.
- •Empyrean Technology's Argus is a hierarchical and parallel physical verification tool designed for ultra-deep submicron IC designs, providing Design Rule Check (DRC) and Layout Versus Schematic (LVS) functionalities, and integrates with other Empyrean tools like Aether and Skipper for a comprehensive design flow.
- •Empyrean Technology, a partially state-owned enterprise founded in 2009, is the largest domestic Electronic Design Automation (EDA) player in China, holding approximately 6% of the country's market share as of April 2024, and was added to the US Entity List in December 2024, which it stated had a "generally controllable" impact.
🛠️ 技術深入
- Huawei's Tau Scaling Law: This new principle shifts the focus from geometric scaling (shrinking transistors) to temporal scaling, optimizing the speed at which signals and data propagate within chips and computing systems.
- Huawei's LogicFolding Architecture: An implementation of the Tau Scaling Law, LogicFolding involves physically folding and stacking logic circuits into multiple layers using ultra-precise hybrid bonding. This technique aims to shorten internal wiring paths, reduce signal propagation delays, and enhance transistor density and circuit performance.
- Performance Claims (LogicFolding): Huawei claims LogicFolding can achieve a 55% increase in transistor density (e.g., from 155 to 238 million/mm² for Kirin 2026 chips) and a 41% improvement in energy efficiency.
- Target Equivalence: Huawei projects that high-end chips designed with the Tau Scaling Law and LogicFolding architecture could achieve transistor density equivalent to 1.4-nanometer processes by 2031.
- Empyrean Argus Capabilities: Argus is a hierarchical and parallel physical verification tool that performs Design Rule Check (DRC) and Layout Versus Schematic (LVS) for ultra-deep submicron IC designs. It is designed to quickly and accurately locate design violations, reduce verification time, and improve productivity.
- Integration: Argus seamlessly integrates with Empyrean's Analog/Mixed-Signal (AMS) design platform, Aether, and its massive layout processing platform, Skipper, providing an end-to-end physical verification solution.
- Debugging: The tool includes a graphical debugging environment (PVE) that allows users to browse and debug verification results, back-annotating errors to layout, schematic, SPICE netlist, and logic viewers.
🔮 前景展望基於引用來源的 AI 分析
China's domestic EDA market share will continue to grow significantly, driven by national policy and industry investment.
Ongoing US sanctions and export restrictions on critical EDA software are compelling China to accelerate its indigenous EDA development, fostering a protected market for domestic players like Empyrean Technology.
Huawei's 'Tau Scaling Law' and 'LogicFolding' could establish a new paradigm for chip performance improvement, reducing reliance on traditional geometric scaling.
As Moore's Law faces physical limitations, Huawei's focus on optimizing signal speed and employing 3D stacking offers an alternative pathway to enhance chip performance and density, potentially mitigating the impact of restrictions on advanced lithography tools.
The global semiconductor supply chain will likely become more fragmented, with distinct regional ecosystems emerging.
The strategic competition and export controls between the US and China are accelerating efforts in both regions to build self-sufficient semiconductor industries, leading to a less integrated and more bifurcated global supply chain.
⏳ 時間線
2009-05
Empyrean Technology founded in Beijing.
2021-11
Empyrean ALPS SPICE simulator certified for Samsung Foundry's 14nm and 8nm technology, becoming a Samsung SAFE™ EDA partner.
2022-07
Empyrean Technology held its Initial Public Offering (IPO) on the Shenzhen Stock Exchange.
2023-03
Empyrean stated its analog tools partially support 5nm processes, and digital tools fully support 7nm processes, amidst Huawei's push for domestic EDA.
2024-12
Empyrean Technology was added to the United States Department of Commerce's Entity List.
2025-03
Empyrean announced plans to acquire a majority stake in Shanghai-based Xpeedic Technology.
📎 來源 (17)
Factual claims are grounded in the sources below. Forward-looking analysis is AI-generated interpretation.
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原始來源： SCMP Technology ↗
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