戴爾：2028 年 AI 加速器記憶體需求 2023 年 625 倍

🔑 增強重點摘要

• •The 2TB per-accelerator memory target is heavily reliant on the transition from HBM3e to HBM4 and HBM4e, which integrate logic dies directly onto the memory stack to improve bandwidth-per-watt efficiency.
• •Dell's strategy involves shifting from standard air-cooled server architectures to direct-to-chip liquid cooling, which is a prerequisite for managing the thermal density of the high-capacity memory stacks required by 2028.
• •Industry analysts note that the 625x growth projection assumes a massive shift toward 'inference-at-the-edge' and 'agentic AI' models, which require significantly larger local context windows than the training-focused models of 2023.

🛠️ 技術深入

• •Memory Scaling: Transitioning from 8-high HBM3e stacks to 12-high and 16-high HBM4 stacks to achieve the 2TB per-accelerator capacity.
• •Interconnect Architecture: Implementation of NVLink Switch systems and PCIe Gen6/7 to handle the increased data movement required by the expanded memory footprint.
• •Thermal Management: Adoption of coolant distribution units (CDUs) and cold plates capable of dissipating 100kW+ per rack to support the high-TDP accelerators.
• •Memory Hierarchy: Integration of CXL (Compute Express Link) 3.0/3.1 to allow for memory pooling and expansion beyond the physical limits of the accelerator's local HBM.

🔮 前景展望基於引用來源的 AI 分析

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