TSMC skips €350M ASML High-NA tool

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💡TSMC rejects €350M tool, signaling sub-1.4nm delays for AI chips.

⚡ 30-Second TL;DR

What Changed

TSMC has no plans to buy ASML High-NA EUV machines.

Why It Matters

This could delay TSMC's advanced node transitions, affecting supply of high-end AI GPUs from Nvidia and others dependent on sub-2nm processes. Competitors like Samsung or Intel may gain edge in lithography adoption.

What To Do Next

Compare Samsung's High-NA EUV roadmap for hedging AI chip production risks.

Who should care:Enterprise & Security Teams

Key Points

•TSMC has no plans to buy ASML High-NA EUV machines.
•Cost per unit exceeds €350 million.
•Tool achieves sub-1.4nm chip manufacturing precision.
•Statement by Co-COO Zhang Xiaoqiang.

🧠 Deep Insight

AI-generated analysis for this event — not the original article.

🔑 Enhanced Key Takeaways

•TSMC is prioritizing the optimization of its existing 'Low-NA' EUV fleet, specifically utilizing multi-patterning techniques to achieve sub-1.4nm nodes without the immediate capital expenditure of High-NA systems.
•Industry analysts suggest TSMC's decision is driven by a 'cost-per-wafer' calculation, where the throughput and yield maturity of current EUV machines currently offer a more favorable ROI compared to the early-stage High-NA infrastructure.
•Intel remains the primary early adopter of ASML's High-NA EUV (EXE:5000/5200 series), positioning its foundry strategy around the early integration of these tools to gain a potential lithography resolution advantage.

📊 Competitor Analysis▸ Show

Feature	ASML High-NA EUV (EXE:5000)	ASML Low-NA EUV (NXE:3800E)
Numerical Aperture	0.55	0.33
Resolution	~8nm	~13nm
Target Nodes	< 2nm (A14/A10)	3nm / 2nm
Estimated Price	> €350 Million	~€150-200 Million
Primary Adopter	Intel	TSMC, Samsung, Intel

🛠️ Technical Deep Dive

High-NA (Numerical Aperture) EUV utilizes a 0.55 NA lens compared to the 0.33 NA of standard EUV, allowing for higher resolution patterning without the need for complex multi-patterning steps.
The EXE:5000 series requires a significant redesign of the wafer stage and reticle handling systems due to the anamorphic lens design, which shrinks the field size by half in one dimension.
High-NA systems require higher power consumption and specialized photoresist materials to compensate for the reduced depth of focus inherent in the higher NA optics.

🔮 Future ImplicationsAI analysis grounded in cited sources

TSMC will face increased process complexity at the 1nm node.

By relying on multi-patterning with Low-NA tools instead of High-NA, TSMC must manage more lithography steps, which increases the risk of overlay errors and reduces overall wafer throughput.

Intel's foundry margins will be under pressure compared to TSMC.

The massive capital depreciation costs associated with early High-NA adoption will weigh heavily on Intel's foundry unit costs compared to TSMC's more mature, lower-cost equipment base.

⏳ Timeline

2023-12

ASML ships the first High-NA EUV system (EXE:5000) to Intel's Oregon facility.

2024-05

TSMC confirms it has successfully produced 2nm test chips using existing Low-NA EUV technology.

2025-09

TSMC begins volume production of its N2 (2nm) process node.

2026-04

TSMC officially announces at the North America Technology Symposium that it will skip High-NA EUV for the immediate future.

🇨🇳Read original article on TechNode

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