TSMC plans sub-1nm chips by 2029

🔑 Enhanced Key Takeaways

• •TSMC is reportedly referring to this sub-1nm node as the 'A10' process, representing the next major evolution following the A16 (1.6nm) and A14 (1.4nm) nodes.
• •The transition to sub-1nm is expected to rely heavily on the adoption of High-NA EUV (Extreme Ultraviolet) lithography machines, which are essential for the increased precision required at these dimensions.
• •TSMC is exploring new materials beyond traditional silicon, such as 2D materials like molybdenum disulfide (MoS2), to overcome physical limitations and leakage issues inherent at the sub-1nm scale.

🛠️ Technical Deep Dive

• •Transition from FinFET to Gate-All-Around (GAA) architectures, specifically TSMC's NanoFlex/Nanosheet technology, is a prerequisite for sub-1nm scaling.
• •Utilization of High-NA EUV lithography (0.55 numerical aperture) to reduce multi-patterning complexity and improve feature resolution.
• •Implementation of backside power delivery networks (BSPDN) to decouple power and signal routing, reducing IR drop and improving transistor density.
• •Research into transition metal dichalcogenides (TMDs) as channel materials to replace silicon, offering better electrostatic control at atomic-scale gate lengths.

🔮 Future ImplicationsAI analysis grounded in cited sources

⏳ Timeline