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TSMC Developing CoPoS Packaging Tech for 2028 Launch
๐กNew glass-based packaging tech from TSMC could redefine AI chip performance and density by 2028.
โก 30-Second TL;DR
What Changed
CoPoS stands for Chip-on-Panel-on-Structure
Why It Matters
This advancement in packaging will likely enhance the thermal and electrical efficiency of future AI accelerators. It represents a critical step in overcoming current limitations in high-performance computing hardware.
What To Do Next
Monitor TSMC's roadmap for glass-substrate integration to plan future hardware procurement for high-compute AI clusters.
Who should care:Developers & AI Engineers
Key Points
- โขCoPoS stands for Chip-on-Panel-on-Structure
- โขIntegrates glass material as both a carrier and substrate component
- โขTargeting mass production by 2028
- โขFeatures a unique three-layer sandwich design
๐ง Deep Insight
Web-grounded analysis with 16 cited sources.
๐ Enhanced Key Takeaways
- โขCoPoS represents a panel-level evolution of TSMC's existing CoWoS (Chip-on-Wafer-on-Substrate) technology, transitioning from circular silicon interposers to square glass or organic panels.
- โขThis shift to rectangular panels significantly boosts substrate utilization from approximately 65% on traditional 12-inch wafers to around 95%, leading to reduced material waste and manufacturing costs, particularly for large AI processors.
- โขNVIDIA's Feynman AI chipset is anticipated to be the inaugural adopter of CoPoS, leveraging the expanded panel area to integrate a greater number of High-Bandwidth Memory (HBM) stacks, potentially up to 12 HBM4 chips, alongside multiple GPU chiplets.
- โขCoPoS is engineered to circumvent the 'reticle limit' by accommodating panel sizes beyond the constraints of traditional 300mm wafers, with proposed formats including 310x310mm, 510x515mm, and even larger dimensions up to 750x620mm under consideration.
- โขThe technology is deemed critical for enabling future generations of ultra-large high-performance computing (HPC) and AI chips, and it facilitates the integration of Co-Packaged Optics (CPO) components such as optical engines and couplers.
๐ ๏ธ Technical Deep Dive
- CoPoS utilizes glass in two distinct capacities: as temporary carriers measuring 310x310mm during processing, and as glass panels (250x250mm for pilot runs, scaling to 510x515mm for mass production) that are subsequently cut into individual glass core substrates.
- The core substrate features a three-layer sandwich structure, comprising a glass core positioned between Ajinomoto Build-up Film (ABF) layers on both sides, often referred to as ABF-GCP.
- Contrary to some misconceptions, the glass in CoPoS does not function as an interposer. The interconnectivity is managed by the chip-side Redistribution Layer (RDL), complemented by Through-Glass Vias (TGV) and copper interconnects embedded within the glass core substrate stack.
- Both glass and ABF layers coexist within the CoPoS structure; glass does not replace ABF. Chips are directly attached to the ABF build-up surface of the glass core substrate.
- CoPoS is a panel-level packaging (PLP) technology, which is expected to deliver higher throughput and lower cost per unit compared to traditional wafer-level packaging (WLP).
- A significant challenge in the mass production of CoPoS, particularly with expanding substrate sizes, is managing warpage issues.
๐ฎ Future ImplicationsAI analysis grounded in cited sources
TSMC will solidify its market leadership in advanced packaging for AI and HPC.
CoPoS offers significant advantages in integration density, cost-effectiveness, and scalability for ultra-large AI chips, making it a critical enabler for next-generation AI accelerators.
The semiconductor industry will see an accelerated shift towards panel-level packaging and glass substrates for high-performance applications.
CoPoS's efficiency gains and ability to overcome the reticle limit will drive broader adoption of panel-level packaging and glass-based solutions by other industry players.
Future AI systems will integrate optical interconnects more deeply within advanced packages.
CoPoS's larger panel platform and available space make it ideal for integrating Co-Packaged Optics (CPO) components, leading to reduced latency and improved power efficiency in AI data centers.
โณ Timeline
2008
TSMC established the Integrated Interconnect and Packaging Technology Integration Department (IIPD).
2011
TSMC developed the first generation of CoWoS packaging technology.
2023
TSMC opened its first all-in-one advanced packaging and testing plant for SoIC and 3DFabric mass production.
2024
TSMC announced production of the world's largest 5.5-reticle-size CoWoS package.
2026
TSMC's CoPoS pilot line is set for completion by mid-year.
2026
TSMC's CoWoS interposer size will extend to 9.5x reticle.
๐ Sources (16)
Factual claims are grounded in the sources below. Forward-looking analysis is AI-generated interpretation.
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