The Race to Commercialize Glass Core Substrates in Packaging

🔑 Enhanced Key Takeaways

•Intel has been a significant driver in the development of glass core substrates, committing to the technology in its advanced packaging roadmap as early as 2023 and showcasing initial prototypes in early 2026.
•Glass core substrates enable significantly higher interconnect density, potentially up to 10 times, and finer redistribution layer (RDL) features, pushing below the 2-micrometer line/space limit of organic substrates.
•The inherent transparency of glass facilitates the integration of co-packaged optics (CPO) and embedded waveguides, which is crucial for dramatically reducing latency and power consumption in data centers and AI systems.
•Despite their advantages, mass production of glass core substrates faces significant challenges, including the material's brittleness, the complexity of reliably fabricating through-glass vias (TGVs) at scale, and the need for advanced inspection systems to detect microscopic cracks.
•The market for glass core substrates is projected for substantial growth, with a Compound Annual Growth Rate (CAGR) of 67.2% from 2028 to 2040, potentially becoming a $13 billion opportunity by 2040.

📊 Competitor Analysis▸ Show

Feature/Property	Glass Core Substrates	Organic Substrates (e.g., ABF)	Silicon Interposers
Warpage	Significantly lower (up to 50% less), ultra-flat.	Higher, increasing with package size.	Higher than glass, 50% more warpage than glass.
CTE Match to Silicon	Tailorable (3-10 ppm/°C), closely matches silicon (2.6 ppm/°C).	Higher (approx. 7-17 ppm/°C), significant mismatch.	Good match to silicon.
Interconnect Density	Enables <2µm line/space RDLs, up to 10x higher density.	Struggles to achieve <2µm line/space.	Very fine wiring, but limited panel size.
Dielectric Constant (Dk)	Low (2.5-6 at 10 GHz), significantly lower than silicon.	Moderate (3.5-4.5 for FR-4, ~7 for OCS).	High (12).
Dissipation Factor (Df)	Very low (0.0005-0.005 at 10 GHz).	Higher (0.015-0.025 for FR-4).	Higher than glass.
Panel Size	Can be fabricated in large panels (e.g., 700x700mm, 510x515mm).	Limited by warpage issues at larger sizes.	Limited to wafer sizes, smaller than glass panels.
Cost	Potentially lower per-unit cost with large panels, but high initial investment.	Generally cost-effective for mainstream.	More expensive than glass.
Brittleness	Inherently brittle, prone to microcracks.	Flexible, less brittle.	Brittle.
Thermal Conductivity	1.0–1.4 W/(m·K), comparable to high-performance organics.	0.3–0.8 W/(m·K) for FR-4, 1.0–2.0 W/(m·K) for high-performance organics.
Optical Transparency	Transparent, enables co-packaged optics.	Opaque.	Opaque.

🛠️ Technical Deep Dive

Material Composition: Typically inorganic silicate glass matrix, such as borosilicate or aluminosilicate, containing 60–70 wt% SiO₂, 10–15 wt% B₂O₃, and 5–10 wt% Al₂O₃.
Thickness: Glass core substrates range in thickness from 50 μm to 500 μm, with ultrathin glass capable of being less than 100 μm.
Coefficient of Thermal Expansion (CTE): Can be precisely tailored from 3 to 10 ppm/°C, allowing for a close match with silicon (2.6 ppm/°C) to minimize thermomechanical stress.
Dielectric Constant (Dk): Borosilicate glass cores exhibit Dk values between 4.6 and 6.2 at 1 GHz, and as low as 2.5-6 at 10 GHz, significantly lower than silicon (12) and organic laminates (3.5-4.5 for FR-4).
Dissipation Factor (Df): Values typically range from 0.003–008 at 1 GHz, and as low as 0.0005-0.005 at 10 GHz, which is considerably lower than organic substrates (0.015–0.025 for standard FR-4).
Thermal Conductivity: Glass core substrates generally have a thermal conductivity of 1.0–1.4 W/(m·K).
Through-Glass Vias (TGVs): These provide vertical electrical paths, with typical resistance values of 5–20 mΩ for 50 μm diameter, 100 μm length vias filled with electroplated copper. Via-to-via capacitance is 0.05–0.15 pF for 50 μm diameter vias with 100 μm pitch.
Redistribution Layers (RDLs): Glass substrates enable the creation of fine-pitch RDLs with line and space features below 2 μm.
Manufacturing Processes: Involves precision micromachining for TGV formation, metallization (e.g., full copper fill or sidewall plating), and patterning of build-up layers using semi-additive processes. Wet etching can be used to form precisely dimensioned cavities in multi-layered glass.
Panel Sizes: Glass can be manufactured in large panel formats, such as 700 x 700mm, 510 x 515mm, or 600 x 600mm, which is advantageous for panel-level packaging.

🔮 Future ImplicationsAI analysis grounded in cited sources

Glass core substrates will become the preferred platform for advanced packaging in AI and HPC, enabling heterogeneous integration and 3D stacking.

Their superior dimensional stability, thermal management, and electrical performance address critical limitations of organic substrates for these demanding applications.

The commercialization of glass core substrates will accelerate the integration of photonic components directly into semiconductor packages.

Glass's optical transparency and low surface roughness make it an ideal medium for embedding optical interconnects, dramatically reducing latency and power consumption.

The glass core substrate market will experience rapid growth, with initial limited-volume production starting around 2028 for high-performance applications.

Industry reports project a significant CAGR of 67.2% from 2028 to 2040, driven by the increasing demands of AI and HPC.

⏳ Timeline

2015

Patent filings for glass core substrates began increasing from players like Toppan, Corning, NCAP, and GlobalFoundries.

2017-06

Corning showcased precision glass solutions for semiconductor packaging, including through-glass vias (TGVs).

2020

Intel emerged as the leading patent assignee in glass core substrates, holding nearly half of the patents in this field.

2023-09

Intel announced its commitment to glass substrates in its advanced packaging roadmap, targeting mass production between 2026 and 2030.

2023-12

Dai Nippon Printing (DNP) launched a pilot line for TGV glass core substrates at its Kuki Plant.

2026-01

Intel debuted the first sample combining EMIB packaging with a glass core substrate at NEPCON Japan.

The Race to Commercialize Glass Core Substrates in Packaging

⚡ 30-Second TL;DR

Key Points

🧠 Deep Insight

🔑 Enhanced Key Takeaways

🛠️ Technical Deep Dive

🔮 Future ImplicationsAI analysis grounded in cited sources

⏳ Timeline

📎 Sources (25)

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