Meta Launches 4 New AI Chips: MTIA

🔑 Enhanced Key Takeaways

• •Next-gen MTIA (v2) uses TSMC 5nm process, operates at 1.35GHz, and delivers 102.4 TFLOPS INT8 GEMM performance with 90W TDP[1][2].
• •MTIA v2 features an 8x8 PE grid with 3.5x dense and 7x sparse compute gains over v1, plus tripled local PE storage and doubled on-chip SRAM[1][2].
• •MTIA v2 supports inference only, not training, and platform-level tests show 6x serving throughput improvement over v1 systems[1][2].
• •MTIA-2 enters production on TSMC 3nm with CoWoS-S packaging and Broadcom support, debuting H1 2026; MTIA-3 follows in H2 2026[5].

🛠️ Technical Deep Dive

• •Architecture: 8x8 grid of 64 processing elements (PEs) connected via mesh network, supporting thread/data/instruction/memory-level parallelism[1][4][7].
• •Memory: 384KB local SRAM per PE (3x v1), 256MB on-chip SRAM (2x v1), up to 128GB off-chip LPDDR5; bandwidths: 1TB/s local per PE, 2.7TB/s on-chip, 176GB/s off-chip[1][2].
• •Performance: 102.4 TFLOPS/s INT8 GEMM, 51.2 TFLOPS/s FP16/BF16, 708 TOPS INT8 with sparsity; vector core 3.2 TFLOPS/s INT8[1][2].
• •Connectivity: 8x PCIe Gen4 (16GB/s host), TDP 90W (2.6x v1), die size 421mm² (25.6x16.4mm), TSMC 5nm[1][2].
• •Deployment: 12 accelerators per Yosemite V3 server with PCIe switches for inter-accelerator communication[4].

🔮 Future ImplicationsAI analysis grounded in cited sources

⏳ Timeline