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Linux Kernel 7.2-rc2 Increases RISC-V CPU Limit to 256

Linux Kernel 7.2-rc2 Increases RISC-V CPU Limit to 256
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💡Critical infrastructure update for RISC-V server adoption, essential for scaling AI and high-performance computing.

⚡ 30-Second TL;DR

What Changed

Default NR_CPUS for RISC-V 64-bit increased from 64 to 256.

Why It Matters

This update signals the maturation of the RISC-V ecosystem for data center and AI infrastructure, allowing developers to deploy more powerful, multi-core RISC-V clusters for large-scale computing tasks.

What To Do Next

If you are building AI workloads on RISC-V hardware, recompile your kernel with the updated NR_CPUS limit to leverage high-core-count server architectures.

Who should care:Developers & AI Engineers

🧠 Deep Insight

AI-generated analysis for this event.

🔑 Enhanced Key Takeaways

  • The increase to 256 CPUs specifically addresses the 'NR_CPUS' configuration limit, which dictates the maximum number of processors the kernel can manage at boot time.
  • This adjustment is part of a broader effort to align RISC-V kernel configurations with other high-performance architectures like ARM64, which often support significantly higher core counts.
  • Developers noted that the memory overhead for increasing this limit is negligible on 64-bit systems, as the kernel uses sparse memory allocation for per-CPU structures.
  • The patch was submitted by the RISC-V Linux maintainers to ensure that upcoming server-grade SoCs, which are expected to exceed the previous 64-core threshold, can boot without custom kernel recompilation.
  • This change specifically targets the 'defconfig' (default configuration) for RISC-V, allowing distributions to support larger hardware out-of-the-box without requiring users to manually adjust kernel parameters.

🛠️ Technical Deep Dive

  • The NR_CPUS parameter defines the compile-time constant for the maximum number of CPUs supported by a specific kernel binary.
  • Increasing NR_CPUS impacts the size of static per-CPU arrays and bitmasks used for CPU affinity and scheduling.
  • On RISC-V 64-bit, the kernel utilizes the 'smp_ops' framework to handle multi-core initialization, which remains compatible with the increased limit.
  • The memory footprint increase is primarily associated with the 'cpumask' structures and per-CPU data sections, which scale linearly with the number of CPUs but remain well within the limits of modern server memory capacities.

🔮 Future ImplicationsAI analysis grounded in cited sources

RISC-V will achieve parity with ARM64 in high-core-count server deployments by 2027.
The removal of artificial software bottlenecks in the kernel allows hardware vendors to scale RISC-V designs to match the core density of established server architectures.
Linux distributions will standardize on 256-core RISC-V kernels for cloud-native environments.
Standardizing the default configuration reduces fragmentation and simplifies the deployment of containerized workloads on RISC-V server hardware.

Timeline

2023-05
RISC-V architecture support in Linux reaches maturity for basic server-side operations.
2024-11
SpacemiT announces the K1 8-core RISC-V SoC, signaling the start of high-performance RISC-V development.
2025-06
Linux kernel developers begin discussions on scaling RISC-V beyond 64 cores to support upcoming multi-chip module designs.
2026-06
Linux Kernel 7.2-rc2 is released, officially incorporating the patch to increase RISC-V NR_CPUS to 256.
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Original source: IT之家