Keller's Anti-GPU AI Chip Revealed
💡Jim Keller's RISC-V AI chip beats GPU inner loops – dev-friendly alternative.
⚡ 30-Second TL;DR
What Changed
NoC grid Tensix cores: 5x RISC-V, 1.5MB SRAM, vector/matrix units
Why It Matters
Challenges GPU monopoly with efficient, cost-effective AI hardware scalable to racks. Appeals to devs seeking alternatives to NVIDIA for custom accelerators.
What To Do Next
Download tt-Metalium SDK and prototype a 32x32 tiled matrix multiply on Tensix.
Key Points
- •NoC grid Tensix cores: 5x RISC-V, 1.5MB SRAM, vector/matrix units
- •Explicit SRAM management for cache-free predictable performance
- •Ethernet 400Gbps multi-chip scaling vs costly NVLink
- •Native 32x32 matrix tiling optimized for DL workloads
🧠 Deep Insight
AI-generated analysis for this event — not the original article.
🔑 Enhanced Key Takeaways
- •Tenstorrent's architecture utilizes a 'dataflow' execution model, which fundamentally differs from the instruction-driven SIMT model of GPUs by allowing data to flow directly between cores without constant memory round-trips.
- •The Wormhole chip incorporates a proprietary 'Packetized' interconnect protocol that allows for seamless scaling across heterogeneous clusters, specifically targeting the reduction of latency in large-scale distributed training.
- •Tenstorrent has shifted its business model to include IP licensing of its RISC-V and Tensix core technology to third-party silicon vendors, aiming to create a broader ecosystem beyond its own hardware.
📊 Competitor Analysis▸ Show
| Feature | Tenstorrent Wormhole | NVIDIA Blackwell (B200) | Groq LPU |
|---|---|---|---|
| Architecture | Dataflow / RISC-V | SIMT / Hopper-Blackwell | Tensor Streaming Processor |
| Interconnect | Ethernet-based (Scale-out) | NVLink (Scale-up) | Proprietary Low-Latency |
| Memory Model | Explicit SRAM (Managed) | HBM3e (Cache-based) | SRAM-centric (Deterministic) |
| Primary Focus | Efficiency/Flexibility | Raw Throughput/Ecosystem | Inference Latency |
🛠️ Technical Deep Dive
- Tensix Core: Comprises a 5-core RISC-V cluster (1 control, 4 worker) paired with a high-performance matrix math engine and a vector engine.
- Memory Hierarchy: Employs a distributed, software-managed SRAM architecture rather than traditional hardware-managed L1/L2 caches to ensure deterministic execution timing.
- Dataflow Engine: Designed to execute graphs of operations where data movement is scheduled at compile-time, minimizing the overhead of instruction fetching and decoding.
- tt-Metalium SDK: Provides a low-level abstraction layer that allows developers to manage data movement and compute scheduling directly on the Tensix cores, bypassing standard driver overhead.
🔮 Future ImplicationsAI analysis grounded in cited sources
⏳ Timeline
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