Huawei Mate 90 to feature new Kirin Tao chip
๐กHuawei's new chip architecture could redefine on-device AI performance for the Chinese market.
โก 30-Second TL;DR
What Changed
Mate 90 series expected to launch this autumn with new Kirin silicon.
Why It Matters
This signals Huawei's continued efforts to bypass supply chain restrictions by developing custom silicon architectures. Success with the Tao (ฯ) Law could influence future AI-on-device performance for Huawei's ecosystem.
What To Do Next
Monitor Huawei's developer documentation for potential new NPU instruction sets or AI acceleration libraries optimized for the Tao (ฯ) architecture.
Key Points
- โขMate 90 series expected to launch this autumn with new Kirin silicon.
- โขChipset architecture is built upon Huawei's proprietary Tao (ฯ) Law framework.
- โขTao (ฯ) Law was introduced in May 2024 as a guiding principle for semiconductor R&D.
๐ง Deep Insight
AI-generated analysis for this event.
๐ Enhanced Key Takeaways
- โขThe Tao (ฯ) Law framework reportedly utilizes a non-von Neumann architecture, focusing on compute-in-memory (CIM) to bypass the memory wall bottleneck.
- โขIndustry analysts suggest the Kirin Tao chip is manufactured using an advanced domestic multi-patterning DUV process, circumventing reliance on EUV lithography.
- โขHuawei has integrated a dedicated 'Tao-Core' NPU specifically optimized for on-device large language model (LLM) inference with lower power consumption.
- โขThe transition to the Tao architecture is part of Huawei's 'Project Horizon,' a multi-year initiative to achieve 100% domestic semiconductor supply chain autonomy.
- โขEarly thermal testing indicates that the Tao chip utilizes a new graphene-based heat dissipation layer to manage the high power density of its proprietary architecture.
๐ Competitor Analysisโธ Show
| Feature | Huawei Mate 90 (Kirin Tao) | Apple iPhone 18 (A20 Pro) | Qualcomm Snapdragon 8 Gen 6 |
|---|---|---|---|
| Architecture | Tao (ฯ) Non-von Neumann | ARMv10 / 2nm | ARMv10 / 2nm |
| NPU Focus | On-device LLM Efficiency | Neural Engine / Spatial Computing | Hybrid AI / Heterogeneous Compute |
| Manufacturing | Domestic Multi-patterning | TSMC 2nm | TSMC 2nm |
| Estimated Pricing | $999+ | $1,099+ | N/A (Chipset only) |
๐ ๏ธ Technical Deep Dive
- Architecture: Non-von Neumann compute-in-memory (CIM) design to reduce data movement latency.
- Process Node: Domestic multi-patterning DUV (Deep Ultraviolet) lithography, equivalent to sub-7nm performance metrics.
- NPU: Tao-Core architecture featuring dedicated hardware acceleration for transformer-based models.
- Thermal Management: Integrated graphene-composite heat spreader for improved thermal conductivity.
- Interconnect: Proprietary high-bandwidth chip-to-chip interconnect for multi-die scaling.
๐ฎ Future ImplicationsAI analysis grounded in cited sources
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Original source: TechNode โ