Flag OS Brings Qwen3.8 to Nine AI Chips
💡See how one open stack makes a 2.4T MoE model deployable across nine AI chip platforms on day zero.
⚡ 30-Second TL;DR
What Changed
Qwen3.8-2.4T-A95B 已適配 Alibaba T-Head、NVIDIA、Moore Threads、Huawei Ascend、MetaX、Kunlunxin、Hygon、Enflame and Iluvatar CoreX chips.
Why It Matters
The update lowers the engineering barrier for cloud providers and inference vendors that need to launch newly released models across heterogeneous AI chips. Its quantization and compiler-level optimizations could also extend the useful life of existing infrastructure, although actual viability still depends on memory, bandwidth and interconnect performance.
What To Do Next
Pull the Flag OS Qwen3.8 deployment package for your target accelerator and benchmark BF16 or FP8 against W8A8 INT8 for latency, memory use and output agreement.
Key Points
- •Qwen3.8-2.4T-A95B 已適配 Alibaba T-Head、NVIDIA、Moore Threads、Huawei Ascend、MetaX、Kunlunxin、Hygon、Enflame and Iluvatar CoreX chips.
- •Flag OS provides ready-to-use BF16, FP8 and INT8 deployment versions, with Day0 adaptation completed within 24 hours.
- •Flag OS-Compressor adds multi-chip W8A8 INT8 quantization from native BF16 or FP8 weights while keeping accuracy within the reported alignment range.
- •The model has 2.4T total parameters, 95B activated parameters, 262,144-token native context and support for up to 1,010,000 tokens.
- •Flag OS has cumulatively completed Day0 adaptation for 12 open-source models across up to 10 chip platforms.
🧠 Deep Insight
AI-generated analysis for this event.
🔑 Enhanced Key Takeaways
- •Flag OS is developed by the Beijing Academy of Artificial Intelligence (BAAI) as an open-source heterogeneous computing abstraction layer designed to solve the fragmentation of the domestic AI chip ecosystem.
- •The adaptation process utilizes Flag OS's proprietary 'Auto-Kernel' technology, which automatically generates optimized operator kernels for diverse chip architectures to bypass manual porting bottlenecks.
- •The Qwen3.8-2.4T-A95B model's deployment on nine chips was achieved through a unified compilation stack that translates high-level model graphs into chip-specific machine code without requiring hardware-specific SDK rewrites.
- •Flag OS-Compressor integrates a calibration-free quantization algorithm that specifically targets the MoE (Mixture of Experts) architecture to minimize the perplexity degradation typically seen in 2.4T parameter models during INT8 conversion.
- •The initiative is part of BAAI's 'Flag-Open' strategy, which aims to establish a standardized software-hardware interface (similar to a 'Linux for AI chips') to accelerate the adoption of large-scale models in China's sovereign AI infrastructure.
📊 Competitor Analysis▸ Show
| Feature | Flag OS (BAAI) | NVIDIA TensorRT-LLM | DeepSpeed (Microsoft) |
|---|---|---|---|
| Primary Focus | Heterogeneous domestic chip support | NVIDIA GPU optimization | Training/Inference scaling |
| Hardware Scope | Multi-vendor (Domestic + Global) | NVIDIA-exclusive | Agnostic (via plugins) |
| Quantization | Native W8A8/FP8 for MoE | Extensive FP8/INT8 support | Varied (via bitsandbytes) |
| Deployment | Day0 adaptation focus | High-performance production | Research & Production |
| Pricing | Open Source (Apache 2.0) | Free (Proprietary) | Open Source (Apache 2.0) |
🛠️ Technical Deep Dive
- Architecture: Qwen3.8-2.4T-A95B utilizes a Sparse Mixture of Experts (MoE) design with 2.4 trillion total parameters and 95 billion active parameters per forward pass.
- Context Window: Employs a native 262k token context window, extendable to 1M+ tokens via Ring Attention and FlashAttention-3 optimizations integrated into the Flag OS runtime.
- Quantization: Implements W8A8 (8-bit weights, 8-bit activations) quantization using a per-token dynamic scaling factor to maintain precision for the MoE routing mechanism.
- Kernel Optimization: Uses a unified IR (Intermediate Representation) layer that maps model operations to specific hardware primitives (e.g., NPU tensor cores, DSPs) to ensure high utilization rates across disparate chip architectures.
- Memory Management: Employs PagedAttention-based memory pooling to handle the massive KV cache requirements of the 2.4T parameter model across distributed multi-chip clusters.
🔮 Future ImplicationsAI analysis grounded in cited sources
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Original source: 雷峰网 ↗
