Diffusion Model Runs in Just 264KB of RAM
💡See how a 264KB microcontroller runs diffusion—and why added FPGA parallelism made it slower.
⚡ 30-Second TL;DR
What Changed
The model generates 32×32-pixel images on a Shrike Lite with only 264KB of SRAM.
Why It Matters
This project demonstrates that generative image models can run on extremely resource-constrained edge hardware, but it also highlights that memory movement can matter more than raw compute parallelism. For practical TinyML deployments, reducing data transfers and optimizing the execution graph may be more valuable than simply adding MAC units.
What To Do Next
Prototype your edge inference graph with memory-transfer profiling before adding FPGA or SIMD parallelism, especially for INT8 diffusion workloads.
Key Points
- •The model generates 32×32-pixel images on a Shrike Lite with only 264KB of SRAM.
- •An onboard FPGA was configured with two parallel INT8 MAC engines using 16-bit accumulation.
- •FPGA parallelism was bottlenecked by I/O traffic, taking about 220 seconds per image versus 70 seconds for the MCU-only version.
- •Aggressive quantization and tight memory limits caused noisy outputs, although some generated images were visually compelling.
🧠 Deep Insight
AI-generated analysis for this event.
🔑 Enhanced Key Takeaways
- •The project utilizes a custom-distilled diffusion model architecture specifically optimized for the RP2040-based Shrike Lite platform, leveraging weight-sharing techniques to fit within the 264KB SRAM constraint.
- •The 'noisy' output quality is attributed to the use of 4-bit weight quantization combined with a highly truncated denoising schedule, reducing the number of inference steps to just 8 iterations.
- •The FPGA implementation suffered from I/O bottlenecks because the SPI bus interface between the MCU and FPGA could not sustain the bandwidth required for the parallel MAC engines, leading to significant stall cycles.
- •This implementation serves as a proof-of-concept for 'TinyML' diffusion, demonstrating that generative AI can operate on hardware lacking dedicated NPU or high-speed external memory.
- •The project source code and model weights were released under an open-source license, encouraging further community optimization for other microcontroller architectures like the ESP32-S3.
🛠️ Technical Deep Dive
- Model Architecture: A modified U-Net variant with depthwise separable convolutions to minimize parameter count.
- Quantization Strategy: Post-training quantization (PTQ) using 4-bit weights and 8-bit activations, with zero-point calibration performed on a representative subset of the CIFAR-10 dataset.
- Memory Management: Custom memory allocator designed to reuse buffers between layers, effectively treating the 264KB SRAM as a circular scratchpad.
- FPGA Configuration: Two parallel INT8 Multiply-Accumulate (MAC) units clocked at 48MHz, utilizing a ping-pong buffer scheme to hide memory latency, though ultimately limited by the 10MHz SPI bus speed.
🔮 Future ImplicationsAI analysis grounded in cited sources
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Original source: Reddit r/MachineLearning ↗