Co-Designed Chip Cuts DeepSeek V4 Inference Costs by 75%

๐กA 75% cost reduction in inference is a massive industry shift. Learn how hardware-software co-design is changing AI.
โก 30-Second TL;DR
What Changed
75% reduction in AI inference costs for DeepSeek V4
Why It Matters
This demonstrates that vertical integration between model architecture and silicon can significantly outperform general-purpose hardware, challenging current GPU dominance.
What To Do Next
Analyze your model's hardware utilization patterns to identify if custom kernel optimization or hardware-specific tuning could yield similar cost savings.
Key Points
- โข75% reduction in AI inference costs for DeepSeek V4
- โขHardware-software co-design between DeepSeek and Huawei
- โขAscend 950DT accelerator performance optimization
๐ง Deep Insight
Web-grounded analysis with 27 cited sources.
๐ Enhanced Key Takeaways
- โขDeepSeek V4 Pro is a 1.6-trillion parameter Mixture-of-Experts (MoE) model that achieves its efficiency by activating only approximately 49 billion parameters per forward pass, significantly reducing inference compute requirements.
- โขThe co-design effort resulted in "Day 0" optimization, ensuring DeepSeek V4 was immediately performant on Huawei Ascend hardware upon its release, facilitated by Huawei's CANN software stack with fused operators.
- โขHuawei's Ascend 950DT accelerator is specifically designed for the memory-intensive decode phase of large model inference, featuring 144GB of Huawei's self-developed HiZQ 2.0 HBM with 4TB/s bandwidth and a 2TB/s interconnect.
- โขDeepSeek V4 incorporates architectural innovations such as a Hybrid Attention Architecture (combining Compressed Sparse Attention and Heavily Compressed Attention) and Manifold-Constrained Hyper-Connections (mHC) to efficiently manage its 1-million-token context window.
- โขDeepSeek V4 Pro is released under the permissive MIT license, making its weights open-source and enabling self-hosting and fine-tuning, which contributes to its significantly lower API pricing compared to proprietary frontier models.
๐ Competitor Analysisโธ Show
| Feature/Metric | Huawei Ascend 950DT | NVIDIA H200/B200 (for comparison) | AMD MI300 Instinct (for comparison) |
|---|---|---|---|
| Target Scenario | Training & Decode-stage Inference | Training & Inference | Training & HPC |
| Memory (HBM) | 144GB HiZQ 2.0 HBM | 141GB HBM3e (H200) | 128GB HBM3 (MI300) |
| Memory Bandwidth | 4 TB/s | 4.89 TB/s (H200) | 6.55 TB/s (MI300) |
| Interconnect Bandwidth | 2 TB/s (chip-to-chip) | NVLink (system-level, higher) | Infinity Fabric (system-level, higher) |
| FP8 Performance | 1 PFLOPS (per chip) | H200: 3.958 PFLOPS; B200: 20 PFLOPS sparse | null |
| FP4 Performance | 2 PFLOPS (per chip) | B200: 40 PFLOPS sparse | null |
| Manufacturing Node | Likely SMIC N+3 (5nm-class) | TSMC 4N (H200), TSMC 4NP (B200) | TSMC 5nm (MI300) |
| Software Ecosystem | Huawei CANN, MindSpore | NVIDIA CUDA, cuDNN, TensorRT | AMD ROCm |
| Availability | Q4 2026 (950DT expected) | H200: late 2024; MI300: early 2023 | MI300: early 2023 |
๐ ๏ธ Technical Deep Dive
-
DeepSeek V4 Model Architecture:
- Type: Mixture-of-Experts (MoE) architecture.
- Parameters: DeepSeek V4 Pro has 1.6 trillion total parameters, with approximately 49 billion active parameters per forward pass. DeepSeek V4 Flash has 284 billion total parameters with about 13 billion active.
- Context Window: Supports a 1-million-token context window.
- Attention Mechanism: Features a Hybrid Attention Architecture combining Compressed Sparse Attention (CSA) and Heavily Compressed Attention (HCA).
- Inter-layer Connections: Utilizes Manifold-Constrained Hyper-Connections (mHC) to stabilize signal propagation and enhance long-context handling.
- Optimizer: Employs the Muon Optimizer for faster convergence and improved training stability.
- Precision: Uses Mixed Precision Training, with MoE expert parameters in FP4 and most other parameters in FP8, incorporating FP4 Quantization-Aware Training (QAT).
- Training: Incorporates Multi-Token Prediction (MTP) during training to improve sample efficiency and output coherence.
-
Huawei Ascend 950DT AI Accelerator:
- Architecture: Based on Huawei's proprietary Da Vinci architecture.
- Die Design: Features a dual-die UMA (Unified Memory Access) architecture, presented as a single device to the operating system.
- Memory: Equipped with 144GB of Huawei's self-developed HiZQ 2.0 HBM.
- Memory Bandwidth: Delivers 4 TB/s memory access bandwidth.
- Interconnect: Provides 2 TB/s interconnect bandwidth between chips.
- Data Formats: Supports multiple low-precision data formats including FP8, MXFP8, XMFP4, and HiF8.
- Software Stack: Leverages the CANN (Compute Architecture for Neural Networks) software stack for heterogeneous compute and optimization, similar to NVIDIA's CUDA.
- Optimization: Employs a three-layer parallel optimization strategy for extreme inference performance.
- Manufacturing Process: Likely manufactured on SMIC's newest N+3 node, which is a 5nm-class process.
๐ฎ Future ImplicationsAI analysis grounded in cited sources
โณ Timeline
๐ Sources (27)
Factual claims are grounded in the sources below. Forward-looking analysis is AI-generated interpretation.
- deepinfra.com
- openrouter.ai
- semianalysis.com
- huaweicentral.com
- scmp.com
- huawei.com
- houdao.com
- jonpeddie.com
- techradar.com
- medium.com
- meetneura.ai
- deepseek.ai
- mindstudio.ai
- mindstudio.ai
- medium.com
- techpowerup.com
- aihardware.ai
- spheron.network
- chozan.co
- substack.com
- techinsights.com
- tomshardware.com
- medium.com
- patsnap.com
- umich.edu
- arxiv.org
- redhat.com
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Original source: Pandaily โ