🏠IT之家•Stalecollected in 9m
China Launches Xiangshan RISC-V Chip Stack & Ruyi OS
💡Open RISC-V high-perf stack enables custom AI chips without licenses
⚡ 30-Second TL;DR
What Changed
Fully open-source Xiangshan: processor core, interconnect, development tools
Why It Matters
Empowers China's RISC-V autonomy for high-end chips, cuts proprietary ISA costs, boosts global open standards voice. Enables flexible AI/server/edge deployments without license fees.
What To Do Next
Clone Xiangshan GitHub repo to prototype RISC-V AI accelerator designs.
Who should care:Researchers & Academics
🧠 Deep Insight
AI-generated analysis for this event.
🔑 Enhanced Key Takeaways
- •The Xiangshan project is spearheaded by the Institute of Computing Technology (ICT) at the Chinese Academy of Sciences, aiming to establish a domestic high-performance computing ecosystem to mitigate risks from international semiconductor export restrictions.
- •Ruyi OS is built upon a hardened Linux kernel optimized specifically for the RVA23 profile, focusing on reducing instruction overhead for high-performance RISC-V cores compared to generic distributions.
- •The Xiangshan architecture utilizes a modular 'chiplet' design philosophy, allowing for scalable integration of heterogeneous accelerators alongside the RISC-V cores to target specific AI and data center workloads.
📊 Competitor Analysis▸ Show
| Feature | Xiangshan (RISC-V) | ARM Neoverse V3 | Intel Xeon (P-Core) |
|---|---|---|---|
| ISA | RISC-V (Open) | ARMv9 (Proprietary) | x86-64 (Proprietary) |
| Licensing | Open Source (BSD/Apache) | Commercial/IP License | Proprietary |
| Ecosystem | Emerging | Mature | Highly Mature |
| Performance | High (RVA23 target) | Very High | Very High |
🛠️ Technical Deep Dive
- Architecture: Out-of-order, superscalar execution pipeline with advanced branch prediction mechanisms.
- RVA23 Profile: Full compliance with the RISC-V RVA23 profile, including support for vector extensions (RVV) and bit-manipulation extensions.
- Interconnect: Proprietary high-bandwidth, low-latency on-chip interconnect designed for multi-core scalability.
- Toolchain: Integrated development environment includes custom compilers, cycle-accurate simulators, and formal verification tools for hardware-software co-design.
🔮 Future ImplicationsAI analysis grounded in cited sources
Xiangshan will achieve parity with mid-range server-grade ARM processors by 2028.
The rapid iteration cycle of the open-source community combined with state-backed funding accelerates the optimization of the RVA23 implementation.
Ruyi OS will become the standard OS for Chinese government-procured RISC-V hardware.
The push for technological sovereignty in China necessitates a unified, domestic software stack to replace foreign dependencies.
⏳ Timeline
2021-06
First generation Xiangshan (Yanqihu) processor core open-sourced by ICT.
2022-07
Second generation Xiangshan (Nanhu) tape-out and performance validation.
2024-03
Announcement of the RVA23-compliant roadmap for the Xiangshan architecture.
2026-03
Official release of the 5th-gen Xiangshan system and Ruyi OS.
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Original source: IT之家 ↗