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Alibaba XuanTie 9 Series Now Supports Android
💡RISC-V is becoming a viable alternative for Android-based AI edge devices; check this for hardware strategy.
⚡ 30-Second TL;DR
What Changed
XuanTie 9 series supports Android 16
Why It Matters
This accelerates the adoption of RISC-V in mobile and edge AI devices, potentially reducing reliance on proprietary architectures.
What To Do Next
Evaluate RISC-V for your next edge AI hardware project to leverage potential cost and architectural flexibility.
Who should care:Developers & AI Engineers
Key Points
- •XuanTie 9 series supports Android 16
- •First RVA23-compliant RISC-V processor to run Android
- •Enables large-scale commercial delivery for RISC-V
🧠 Deep Insight
Web-grounded analysis with 18 cited sources.
🔑 Enhanced Key Takeaways
- •Android maintainers have initiated mature support for RISC-V, specifically identifying the RVA22 profile, along with vector and vector cryptography extensions, as crucial for achieving expected performance on RISC-V CPUs.
- •Google and Qualcomm have previously announced collaborations to integrate the Wear OS platform with RISC-V architecture, targeting wearables as an initial device category for deployment.
- •Alibaba's DAMO Academy has developed and released over 10 XuanTie processors, which have subsequently powered more than 200 mass-produced chips and nearly 1,000 end products across diverse sectors including servers, robotics, and AI terminals.
- •The RVA23 profile, to which the XuanTie 9 series is compliant, mandates the inclusion of the RISC-V Vector Extension (RVV), thereby elevating structured, explicit parallelism to a foundational architectural status.
- •Alibaba's flagship XuanTie C950, a 5nm RISC-V core, features an 8-instruction decode width and a 16-stage pipeline, specifically engineered to handle demanding agentic AI workloads.
🛠️ Technical Deep Dive
- XuanTie 9 Series (e.g., C910/XuanTie-910):
- 64-bit, multi-core processor, with up to 4 cores per cluster.
- Features a 12-stage deep pipeline, out-of-order, multi-issue superscalar architecture.
- Achieves a maximum clock frequency of 2.5 GHz in a 12nm FinFET process technology.
- Implements the RV64GCV instruction set, including the base 64-bit RISC-V ISA (RV64G), compact 16-bit instructions (C), and vector extensions (V).
- Supports the 0.7.1 stable release of the RISC-V vector extension specification.
- Includes custom extensions for arithmetic operations, bit manipulation, load and store, TLB, and cache operations.
- Supports multi-core multi-cluster Symmetric Multiprocessing (SMP) with cache coherence.
- Equipped with 32/64 KB L1 instruction and data caches, and a shared L2 cache configurable up to 8 MB.
- Utilizes an SV39 Memory Management Unit (MMU), compatible with the RISC-V Linux specification.
- Incorporates XuanTie Instruction Extension (XIE) and XuanTie Memory Attribute Extension (XMAE) technologies.
- XuanTie C950 (Flagship):
- Built on a 5 nm RISC-V core.
- Features an 8-instruction decode width and a 16-stage pipeline.
- Supports over one-thousand in-flight instructions.
- Achieves clock frequencies peaking near 3.2 GHz.
- Includes on-chip vector and matrix units optimized for sparse and dense sequences.
- Provides eight DDR5 channels and PCIe 5.0 lanes.
- Incorporates dedicated engines for accelerating tokenization and transformer attention math.
- RVA23 Profile:
- Designed for 64-bit application processors intended to run rich operating system stacks and a substantial number of third-party binary applications.
- Mandates support for the RISC-V Vector Extension (RVV) and Hypervisor extensions.
- Aims to ensure portability and binary compatibility of software across different hardware implementations.
- New mandatory extensions in RVA23U64 include Vector Extension (V), Zvfhmin, Zvbb, Zvkt, Zihintntl, Zicond, Zimop, and Zcmop.
- Mandates the Zifencei instruction for instruction-cache coherence.
🔮 Future ImplicationsAI analysis grounded in cited sources
RISC-V will significantly expand its presence in high-performance computing and AI agent applications.
The RVA23 profile's mandatory vector and hypervisor extensions, coupled with Alibaba's C950 targeting AI agent workloads, position RISC-V for demanding computational tasks beyond traditional embedded uses.
The Android ecosystem for RISC-V will mature rapidly, leading to more commercial devices.
Google's mature support for RISC-V in Android, including plans for NDK ABI finalization and public emulators, combined with Alibaba's successful Android 16 adaptation, will accelerate developer adoption and product launches.
China's semiconductor industry will achieve greater self-reliance through RISC-V.
Alibaba's substantial investment and leadership in RISC-V development, driven by a desire for architectural sovereignty and to counter US export controls, directly contributes to China's domestic chip development goals.
⏳ Timeline
2018
Alibaba launched the XuanTie series of RISC-V processors.
2020-12
Alibaba's T-Head released an open-source Android 10 port for RISC-V chips.
2022-11
Google announced its decision to accept RISC-V patches for Android.
2024-03
The RVA23 profile, which the XuanTie 9 series is compliant with, was ratified by the RISC-V International Foundation.
2025-06
Android 16 was released by Google.
2026-03
Alibaba's DAMO Academy unveiled the XuanTie C950 and C925 processors, targeting AI-Agent applications.
📎 Sources (18)
Factual claims are grounded in the sources below. Forward-looking analysis is AI-generated interpretation.
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Original source: 36氪 ↗