三星1c DRAM良率超80%，HBM4逼近60%

🔑 增強重點摘要

• •Samsung redesigned its 1c DRAM process under new leadership by increasing peripheral circuit line width to prioritize stability over cost, addressing prior lag behind SK hynix and Micron who used advanced 1b DRAM for HBM3E.[1]
• •Samsung pursued dual strategies for 1c DRAM improvement: modifying prior 1a/1b designs or full redesign with larger chips for higher yields, though at increased cost due to more wafer usage.[1][2]
• •HBM4 logic die, fabricated on Samsung's 4nm foundry process, achieved over 80% mass-production yield, exceeding 90% in early tests before performance tweaks, enabling stable commercialization.[3]
• •NVIDIA requested Samsung to boost 1c DRAM yields for reliable HBM4 supply, as 1c will extend to HBM4E, prompting design changes amid competitors' mature 1b DRAM processes over 80% yield.[3]

🛠️ 技術深入

• •1c DRAM is sixth-generation 10nm-class DRAM, one generation ahead of competitors' 1b (5th-gen 10nm) used in HBM3E core dies.
• •Redesign increases peripheral circuit line width for chip stability; full redesign option yields larger chips with higher production rates but elevated costs from increased wafer consumption.
• •HBM4 logic die uses Samsung Foundry's 4nm process as the 'brain' for stacking and control.

🔮 前景展望AI analysis grounded in cited sources

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