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英特爾 18A 製程實測:M0 間距 36nm、GAA 間距 76nm

英特爾 18A 製程實測:M0 間距 36nm、GAA 間距 76nm
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🏠閱讀原文: IT之家
#gaa-transistors#power-via#process-nodeintel-panther-lake

💡Intel 18A real metrics show 36nm M0/76nm GAA—yield challenges for AI infra designers

⚡ 30-Second TL;DR

有什麼變化

晶片尺寸約 110mm²,所有區域採用 HP 庫(G50H180 邏輯,0.023μm² SRAM)

為什麼重要

揭示 Intel 先進節點的實際妥協,延遲完整背面供電優勢並凸顯整合挑戰,與 TSMC 相比。影響依賴 Intel 代工的高性能運算 AI 硬體設計師。

下一步行動

Benchmark Intel 18A HP library densities against TSMC N2 for AI accelerator layouts.

誰應關注:Developers & AI Engineers

關鍵要點

  • 晶片尺寸約 110mm²,所有區域採用 HP 庫(G50H180 邏輯,0.023μm² SRAM)
  • M0 金屬間距 36nm(HP)對比 32nm(HD),15 前段 + 6 後段金屬層
  • GAA 間距邏輯 76nm / SRAM BL 52nm,Power Via 僅限邏輯因間距限制
  • 材料:鎢 V0/V1,銅 M0;GAA 具內部間隔層
  • 良率爬坡於 HP 庫,14A 以 BSCON 實現 SRAM Power Via

🧠 深度解析

背景與延伸:來自公開資料,非原文內容。引用 6 個來源。

🔑 增強重點摘要

  • Intel 18A process node achieved first commercial deployment in Panther Lake (Core Ultra Series 3) launched at CES 2026, implementing RibbonFET gate-all-around transistor architecture with 76nm GAA gate spacing for logic cells[1]
  • PowerVia backside power delivery system delivers 36% improvement in power integrity and enables 15% higher clock speeds on logic circuits, though implementation limited to logic due to pitch constraints in SRAM regions[1]
  • Panther Lake die utilizes HP (high-performance) library across all regions with 36nm M0 metal spacing, featuring 15 FEOL and 6 BEOL metal layers with tungsten and copper interconnects[1]
  • Intel 18A represents transition from FinFET to GAA architecture, achieving 20% power reduction at equivalent performance levels compared to previous generation nodes[1]
  • Future Intel 14A node expected to enable PowerVia support in SRAM through BSCON (backside contact) technology, addressing current spacing limitations that restrict backside power delivery to logic-only implementation[1]
📊 競品分析▸ Show
FeatureIntel 18A (Panther Lake)AMD Zen 6 (EPYC Turin)TSMC N2
Process Node18A (Intel)5nm equivalentN2
Transistor ArchitectureRibbonFET (GAA)FinFETGAA
Power DeliveryPowerVia (logic only)TraditionalBackside power (limited)
M0 Spacing36nm (HP)Not disclosedNot disclosed
Performance CoresCougar CoveZen 6N/A
AI Performance180 TOPS (platform)AVX512 extensionsN/A
Battery Life (Mobile)27 hours video playbackN/AN/A

🛠️ 技術深入

Transistor Architecture: RibbonFET implements gate-all-around (GAA) design with 76nm gate spacing in logic, 52nm in SRAM bitline, replacing traditional FinFET with four-sided channel control[1]Power Delivery: PowerVia moves power routing to wafer backside, separating from data signals on top surface; limited to logic circuits due to 36nm M0 pitch constraints in SRAM regions[1]Interconnect Stack: 15 FEOL (front-end-of-line) and 6 BEOL (back-end-of-line) metal layers; V0/V1 vias use tungsten, M0 and higher use copper[1]Die Configuration: Panther Lake flagship (Core Ultra X9 388H) features hybrid architecture with Cougar Cove performance cores and Darkmont efficiency cores, integrated Xe3 Battlemage GPU, and NPU 5 delivering 50 NPU TOPS[1]Platform AI Performance: Xe3 GPU + NPU 5 combination achieves 180 TOPS total, enabling local LLM execution (Llama 3 class models)[1]Yield Status: HP library ramping in production; SRAM PowerVia deferred to 14A node via BSCON technology implementation[1]

🔮 前景展望AI analysis grounded in cited sources

Intel 18A's successful RibbonFET and PowerVia implementation establishes new manufacturing baseline for AI-capable mobile processors, positioning Intel to compete with Apple and Qualcomm in battery life and performance density. The 27-hour video playback claim reclaims 'Battery Life King' title from competitors[1]. Deferral of SRAM PowerVia to 14A node indicates yield challenges at current node, suggesting 18A production ramp may face constraints through 2026. Panther Lake's 180 TOPS AI performance enables on-device LLM inference, critical for Copilot+ PC certification and enterprise AI adoption. Future 14A node with BSCON technology promises comprehensive backside power delivery across all circuit types, potentially enabling further power efficiency gains and higher clock speeds. Intel's 18A-P and 18A-PT variants targeting datacenter (Clearwater Forest Xeon) and foundry customers signal broader ecosystem adoption beyond mobile, though competitive pressure from TSMC N2 and AMD's Zen 6 remains significant.

時間線

2024-08
Intel Panther Lake powered on, confirmed on-track for 2025 production on 18A process node
2025-08
Panther Lake production begins; yield concerns reported with three times higher defect rates on 18A
2025-12
Panther Lake production ramps in late 2025 ahead of CES 2026 launch
2026-01
Intel launches Core Ultra Series 3 'Panther Lake' at CES 2026, first commercial 18A process deployment with RibbonFET and PowerVia technologies
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